Principal Engineer/Manager, ASIC Physical Design
2 weeks ago
Principal Engineer/Manager, ASIC Physical Design
About InnoPhase, Inc.
INNOPHASE
is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
As a
Principal Engineer/Manager, ASIC Physical Design
, you will
be responsible for providing technical leadership in developing novel/game-changing cellular infrastructure radio
and ASIC solutions.
You will be a key contributor to our solutions features, architectures, device functional specifications, and performance.
Your primary responsibilities include providing technical guidance on block physical implementation to a multi-site team of engineers, determining project requirements, driving the chip integration of large SOCs, efficiently delegating and tracking tasks, and supporting other discipline teams to bring the SoC device to successful mass production.
This full-time position is in San Jose, CA, but either the Irvine or San Diego location is also an option.
Key Responsibilities:
Drive chip level integration of digital and analog IPs and provide technical direction
Contribute to all aspects of ASIC integration effort including floor planning, clock and power distribution, global signal planning, I/O planning, and hard IP integration
Perform block-level implementation using place and route techniques to meet area/timing and power requirements when needed.
Drive clock tree planning and implementation to achieve the best energy, performance, and area goals
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Work directly with the Synthesis/Timing Team to ensure Design closure
Manage quality deliverables and execute excellent physical designs in a timely manner
Job Qualifications:
MS in Electrical Engineering plus 20 or more years of experience in ASIC physical design
Significant experience in chip assembly process of large SOCs in advanced process nodes
Able to contribute as an individual contributor on block level physical implementation, P&R
Deep understanding of Physical Design, Integration, STA, and Physical Verification
Expert in full-chip Formal verification, signal EM, IR-drop analysis, STA, and physical verification.
Hands-on experience in block-level floor-planning, power planning, placement, clock tree synthesis, routing, LVS/DRC/ERC, timing closure, signoff, and engineering change orders (ECO's)
Knowledge and skills in optimizing PPA through floor-planning, placement and timing constraints, useful skew, and similar techniques
Experience with the Cadence digital EDA toolset (Innovus / Quantus / Tempus / Conformal)
Ability to use scripting languages to automate process flow
Team player with good interpersonal and communication skills
Experience with DFT flow
Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience
Familiarity with industry-standard interfaces
Compensation and Benefits:
At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.
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