ASIC Design Engineer
1 month ago
We are actively seeking skilled UPF specialists to construct and validate power intent definitions at the IP/SOC level for cutting-edge, high-performance, power-efficient SOC designs. This pivotal role will drive forward a state-of-the-art power design initiative, collaborating across disciplines and playing a crucial role in expediting product launches.
Qualifications
We're in search of candidates with a solid background in ASIC design methodology, particularly focusing on power definition. Candidates should be well-versed in power intent definition, implementation, and verification workflows. Proficiency in the entire RTL2GDS flow (including RTL simulation, equivalence checking, synthesis, place and route, and intent validation) is essential. Successful candidates will be responsible for ensuring comprehensive coverage of power intent across static and dynamic checking methodologies. Additionally, they should comprehend the software and system-level interactions that influence power consumption.
Requirements
Candidates should be adept at initiating power intent checking workflows for new projects and proficient in scripting languages such as Tcl and Python.
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