![OPENEDGES Technology, Inc.](https://media.trabajo.org/img/noimg.jpg)
Design Verification Engineer
1 month ago
OPENEDGES develops AI Edge Computing semiconductor IPs, so that more people can enjoy AI technology closer.
Have you got what it takes to succeed The following information should be read carefully by all candidates.
???? Location: San Jose, CA, USA or Austin, TX, USA
???? Position: Design Verification Engineer
OPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs all together in one place since 2017.
Job Summary:
OPENEDGES is seeking highly motivated, qualified individuals to join the Design Verification (DV) team for our upcoming configurable cache coherent Network-on-Chip (NoC) program. This exciting position based in San Jose, CA, or Austin TX, offers opportunities to work within a veteran team of industry experts to solve state of the art DV challenges as they apply to the complexities of a coherent mesh fabric. Currently we are staffing the team for several levels and are interested in folks who are attracted to working in entrepreneurial environments with small to mid-size teams. We are looking for team players with alignment for these types of products with aggressive schedules, have hands-on experience in all aspects of DV efforts, and can bring to bear their expertise in making our effort a success.
Roles & Responsibilities:
The successful Design Verification Engineer (DVE) will be responsible for:
- Collaborating with architecture/design teams to understand the NoC design
- Apply state of the art methods to author comprehensive DV plans/schedules/tracking
- Establish and/or contribute to required DV flows/methodologies
- Work with vendors to integrate UVM-based verification IP into a complete testbench solution
- Determine and implement required UVM-based correctness checking
- Creating a UVM-based constrained random stimulus suite to achieve high coverage
- Implement UVM-based tracking methods to acquire and track coverage to closure
- Hands-on debugging simulation fails down to root-cause (Verilog RTL)
- Demonstrating good communication skills, works well in small dynamic teams
Required Qualifications:
The ideal DVE candidate will have a reasonable mix of the following credentials:
- MSEE/MSCE +5 years, BSEE/BSCE +(5-10) years of relevant experience/track record
- Knowledge/experience in the following areas: 1) Cache coherent memory architectures and NoC designs, 2) AMBA buses: CHI, CSL, AXI(n), ACE, APB, 3) Standard IP: DDR(x), PCI, PCIe, ARM, X86, RISC-V
- Hands-on development of testbenches using Verilog, SV/UVM, RAL, SVA, ABV, UPF, XProp
- Experience in installing/configuring vendor IP for highly integrated testbench design
- Experience using industry standard toolsets
- Scripting languages: PERL/Python/Tcl/XML
Preferred Qualifications:
- Formal verification methods, emulation experience
Benefits:
- Medical, dental, and vision benefits
- Life insurance
- 401k retirement plan
- Paid time off, paid holidays, sick leave, etc.
We have other current jobs related to this field that you can find below
-
Design Verification Engineer
1 day ago
San Jose, United States Synapse Design Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description :: Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CA Staff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and...
-
Design Verification Engineer
3 weeks ago
San Jose, United States Synapse Design Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description :: Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CA Staff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog...
-
Design Verification Engineer
1 week ago
San Jose, United States Synapse Design Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description :: Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CA Staff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog...
-
Design Verification Engineer
3 weeks ago
San Jose, United States Synapse Design Inc. Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description ::Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CAStaff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and...
-
Design Verification Engineer
3 weeks ago
San Jose, United States Synapse Design Inc. Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description ::Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CAStaff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and...
-
Design Verification Engineer
3 weeks ago
San Jose, United States Synapse Design Inc. Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description ::Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CAStaff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and...
-
Design Verification Engineer
3 weeks ago
San Jose, United States Synapse Design Inc. Full timeSynapse ( A Quest Global Company) is seeking talent for mixed signal design verification engineer job position. Below is the job description ::Title :: Analog Mixed Signal Design Verification Engineer Location :: San Jose,CAStaff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and...
-
Design Verification Engineer
4 weeks ago
San Jose, United States Synapse Design Full timeSynapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and resolving...
-
Design Verification Engineer
2 months ago
San Jose, United States Synapse Design Full timeSynapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and resolving...
-
digital design and verification engineer
4 days ago
San Jose, California, United States Cadence Design Systems Full timeAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.The Engineers primary responsibility will be the RTL design and verification. Responsibilities on the design side will include function definition, micro architectural specification, design, simulation, verification, and synthesis at module and...
-
Senior Design Verification Engineer
2 days ago
San Francisco, United States Synapse Design Full timeTitle :: Sr. Design Verification EngineerLocation :: Bay Area, CA NOTE: "Minimum 06 Years of exp required" Minimum experience:• Create test benches in SystemVerilog with UVM• Utilize advanced verification techniques• Write tools and scripts to enhance the verification process Qualifications and requirements:• BS, MS in computer science or...
-
Design Verification Engineer
2 months ago
San Jose, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert.Experience:: +10 yearsRequirements:Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.Experience in triaging regressions, debugging, and resolving down...
-
Design Verification Engineer
2 months ago
San Jose, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert.Experience:: +10 yearsRequirements:Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.Experience in triaging regressions, debugging, and resolving down...
-
Design Verification Engineer
2 months ago
San Jose, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert.Experience:: +10 yearsRequirements:Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.Experience in triaging regressions, debugging, and resolving down...
-
Design Verification Engineer
2 months ago
San Jose, CA, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and...
-
Design Verification Engineer
4 weeks ago
San Diego, United States Verilab Full timeJob Description Job Description Job Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel,...
-
Design Verification Engineer
4 weeks ago
San Diego, United States Verilab Full timeJob DescriptionJob DescriptionJob SummaryWe invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more.You will have the opportunity to travel,...
-
Design Verification Engineer
4 weeks ago
San Diego, United States Verilab Full timeJob Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel, present at conferences, win...
-
Design Verification Engineer
4 weeks ago
San Diego, United States Verilab Full timeJob Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel, present at conferences, win...
-
Design Verification Engineer
3 weeks ago
San Diego, United States Verilab Full timeJob Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel, present at conferences, win...