Design Verification Engineer
Found in: Appcast Linkedin GBL C2 - 2 weeks ago
Synapse Design is looking forward to hire Design Verification Engineer expert.
Experience:: +10 years
Requirements:
- Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.
- Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.
- Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues.
- Experience building UVM scoreboards for NOC based Switching, Routing networks .
- Understanding of DFT/X and Post Silicon ATE correlation.
Preferred Skills
- Ability to create and connect C/C++ reference models via DPI for RTL-to-C checking.
- Experience with Formal Verification using tools like: Cadence JasperGold, Synopsys VCF or similar.
- Good understanding of number formats Floating-point arithmetic(FP8,FP16 FP32) and implementation.
- Knowledgeable in RISCV/ARM assembly programming
- Gate-level simulation experience
- Knowledge of UPF based simulations.
If interested, please share your resume at shashank.verma@quest-global.com and let me know your best time to reach.
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Design Verification Engineer
2 weeks ago
San Jose, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert.Experience:: +10 yearsRequirements:Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling.Experience in triaging regressions, debugging, and resolving down...
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Design Verification Engineer
Found in: Jooble US O C2 - 2 weeks ago
San Jose, CA, United States Synapse Design Inc. Full timeSynapse Design is looking forward to hire Design Verification Engineer expert. Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging regressions, debugging, and...
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