Principal Design Engineer, IC Layout

4 weeks ago

Seattle, United States Impinj Full time

Team Overview: Today’s Internet of Things (IoT) applications rely on item-level data enabled by RAIN RFID technology. Impinj, the world’s #1 provider of RAIN RFID products and solutions, is expanding our Layout Design Engineering group, an integral part of the Silicon Engineering department. This will be a high visibility role and will be key in the success of the department and company. The principal layout designer will work with circuit design team members to convert block / IP schematics into full custom layouts of analog, digital and mixed-signal designs and will lead the full chip floorplan development, integration, and tape-in for industry leading RFID endpoint IC and RFID Reader IC products. What will you do: Leverage your experience with Tops Down Bottoms Up (TDBU) floorplan methodology to complete on-schedule layout development and tape-in of power efficient ICs. Collaborate with circuit designers and block level layout designers to create an initial tops down IC floorplan with estimated block sizes / block pin rings, estimated inter-block routes and full chip channels. Work closely with the circuit design team on power supply strategy, and signals distribution between blocks. Follow the documented floorplan methodology ensuring appropriate blocks and full chip channels/signal routes reside in the appropriate level of hierarchy to ensure efficient IC layout development and Tape-in. Work with program managers to coordinate layout and floorplan activities at both the block/IP and top-level layout integration and verification to ensure development and tracking to a predictable schedule. Conduct layout reviews for power/ground routing, electro migration, matching, and signal coupling/integrity. Complete full chip activities such as seal-ring integration, bump integration, dummy fill, full chip DRC, LVS, density and DFM checks. Lead and coordinate the tape-out process, collaborating with cross-functional teams, such as design, verification, packaging, manufacturing and foundry to ensure a successful and timely tapeout of the chip. Perform detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, ADC/DAC, baseband filters, phase shifters, bias, and power management IPs. Apply expertise of the Cadence schematic and layout editors and Cadence and Mentor Layout verification tools to deliver correct and robust layout that meet Area, Robustness, Quality, and performance guidelines. Interpret LVS, DRC, and DFM reports to complete layout projects and debug complex verification issues. What you will bring: 12+ years of industry experience in custom Analog RF and mixed-signal layout with experience developing and leading complex layout ICs at the cell, block and chip levels and a consistent track record of taping out multiple chips that have gone into production. Understanding of semiconductor manufacturing processes and foundry technologies. Good understanding of the challenges in analog layout – noise coupling effects, matching, RC delay, and parasitic is expected. Proficient in layout techniques for device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing. Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, WPE. Understanding of dummy fill, ESD and all related reliability requirements. Strong analytical and problem-solving skills to identify and address layout-related issues efficiently. Meticulous attention to detail, ensuring the highest level of accuracy and quality in all layout designs (designs are properly verified, validated, and tested for long-term reliability and zero defect). Ability to identify failure-prone circuit and layout structures and actively work with circuit designers to resolve problems. Expert knowledge of Analog layout tools and methodologies used in all layout design phases. Expert knowledge of industry standard EDA tools from Cadence, Mentor - Cadence Virtuoso Schematic and Layout tools and cadence/mentor layout verification tools. PVS, and Mentor Graphics Calibre DRC and LVS and good proficiency in the Linux environment. High level of proficiency in interpreting DRC and LVS error reports. Ability to write SKILL code or PERL Scripts is a plus but is not required. Experience with layout design rules and layout design flows for process technology nodes from 90nm to 16nm. Expert in physical implementation of cells, Analog blocks / IPs and leading the SOC level integration / assembly. Expert in floor planning, Block placements, pin ring generation, block level routing and top-level integration & chip assembly and layer generation. Experience in delivering advanced floorplan strategies and expertise in running and debugging DRC and LVS verification across intermediate layout hierarchies and at full chip level required. Capability to lead other layout engineers as the top-level Floorplan / IC integration owner. Excellent communication and interpersonal skills to collaborate effectively with cross-functional teams -Analog circuit engineers, Process design engineers, digital engineers and other layout team members. Excellent time and technical task management skills. #J-18808-Ljbffr

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