ASIC Physical Design Engineer: RTL-to-GDS
Save this job and keep your search organized
Create a free account to save jobs, create alerts and return to this listing from your dashboard.
By continuing, you agree to our Terms & Privacy Policy.
Neetha Consulting LLC is seeking a Physical Design Engineer in Cupertino, CA for a full-time role. The position involves leading RTL to GDS implementations through the ASIC flow, and managing floorplanning, placement, clock tree synthesis, routing, and signoff readiness.
The candidate will optimize high-performance, low-power designs at advanced nodes (TSMC N5/N4P/N3), perform timing closure, UPF, and power planning while driving automation via Python/Perl/TCL scripts.
#J-18808-Ljbffr