RTL Design Engineer — ASIC

3 weeks ago

Cupertino, CA, United States Apple Inc. Full-time $150,000 - $225,000

Apple Inc. in Cupertino, California, seeks a senior RTL/ASIC designer to deliver complex digital IPs for PMICs. You will design digital logic in SystemVerilog, collaborate with cross-functional teams, and drive PPA-aware implementation from RTL to gate-level.

The role involves clock domain crossing and reset domain checks, signoff duties, and scripting in Perl/Python, with opportunities for relocation and growth in a leading hardware team.

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