Senior Design Verification Engineer

Eximietas Design is a leading technology consulting and solutions development firm specializing in VLSI, Cloud Computing, Cyber Security, and AI/ML. Our engineering leadership team brings decades of experience from top-tier semiconductor and technology companies. With a deep commitment to innovation and excellence, we deliver cuttingedge solutions that help...

A leading technology consulting firm is seeking a Mid-Senior Design Verification Engineer to enhance UVM testbench components for IP, Subsystem, or SoC. The ideal candidate will have over 10 years of experience in Design Verification, a Bachelor's degree in Computer Science or Electrical/Electronics Engineering, and proficiency in SystemVerilog and UVM. This...

Senior IC Design Verification Application Engineer page is loaded## Senior IC Design Verification Application Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R51976## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**At Cadence, we hire and develop...

Position Overview Acceler8 Talent is looking for a Senior Design Verification Engineer to join a high-performing Mountain View-based startup, helping them create best-in-class silicon for high-performance and sustainable Generative AI. If you’re looking to make an impact in this exciting age of technological advancement, this opportunity is not to be...

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Role: Familiarity with RTL design in Verilog and System Verilog Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.Develop test plan to verify Hardware building blocks, Design macros...

Job Title: Verification Engineer (SystemVerilog/UVM)📍 Location: Sunnyvale, CA or Austin, TX5–14 years experienceResponsibilitiesDevelop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC-level testing.Understand design specifications and create comprehensive test plans based on functional and architectural...

Job Title: Verification Engineer (SystemVerilog/UVM)📍 Location: Sunnyvale, CA or Austin, TX5–14 years experienceResponsibilitiesDevelop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC-level testing.Understand design specifications and create comprehensive test plans based on functional and architectural...

Job Title: Verification Engineer (SystemVerilog/UVM) Location: Sunnyvale, CA or Austin, TX5–14 years experienceResponsibilitiesDevelop and maintain UVM/SystemVerilog-based verification environments for IP, subsystem, and SoC-level testing.Understand design specifications and create comprehensive test plans based on functional and architectural...

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary: This individual independently plans, performs the moderately-defined responsibility for the development of test plans and the functional verification on hardware at the IP, sub-system, SoC and system/architecture level for wireless and wired...

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the development of test plans and the functional verification on hardware at the IP, sub-system, SoC and system/architecture level for wireless and...