Design Verification Engineer
3 weeks ago
G-Research is a leading quantitative research and technology firm, with offices in London and Dallas. We are proud to employ some of the best people in their field and to nurture their talent in a dynamic, flexible and highly stimulating culture where world-beating ideas are cultivated and rewarded.
This is a hybrid role based in our new Dallas infrastructure hub where we work on the latest technologies in a cutting-edge environment.
The role:
G-Research is seeking a Design Verification Engineer to join our world-class Hardware Engineering function.
As a Design Verification Engineer, you will provide technical expertise, support and guidance around hardware verification using industry standard tools and methodologies.
As a key part of our FPGA design team, you will oversee the effective application of verification to complex design projects.
You will have excellent knowledge of industry standard interfaces and build tools, and be comfortable writing test plans, creating test benches and analyzing code coverage.
Key responsibilities of the role include:
Developing System Verilog based VMM/UVM test bench environments
Developing assertion and functional coverage verification environments
Developing co-simulation environments to verify between C/C++ models and RTL modules
Writing test plans, creating test bench specifications and analyzing code coverage plans
Implementing constrained-random sequences, agents, and environments using the UVM methodology
Developing and maintaining complex verification environments using different methodologies, such as UVM, SV and C++
Debugging failing simulations to RTL level
Who are we looking for?
We are looking for an engineer with extensive experience of large FPGA and ASIC design to join our Hardware Engineering function.
The ideal candidate will have the following skills and experience:
Knowledge of industry-standard interfaces, such as Avalon and AXI
Experience with industry-standard build tools, including version control
Extensive experience with large FPGA/ASIC designs
Proficient in programming, for example Python and C/C++
The following experience would also be beneficial:
Knowledge of QuestaSim environment
A Fintech background
Why should you apply?
Market-leading compensation plus annual discretionary bonus
Lunch provided in the office (via GrubHub)
Informal dress code and excellent work/life balance
Excellent paid time off allowance of 25 days
Sick days, military leave, and family and medical leave
Generous 401(k) plan
16-weeks' fully paid parental leave
Medical and Prescription, Dental, and Vision insurance
Life and Accidental Death & Dismemberment (AD&D) insurance
Employee Assistance and Wellness programs
Generous relocation allowance and support
Great selection of office snacks, and hot and cold drinks
On-site gym and car parking%{{advertiserId}}% %%{{category}}%%
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