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Acceler8 Talent | ASIC Design Engineer

1 month ago

mountain view, United States Acceler8 Talent Full time

Acceler8 Talent is actively seeking an experienced Microarchitect and RTL design engineer to contribute to a team shaping the best-in-class silicon solutions for high-performance and sustainable GenAI.


In this role, you will work with an exceptional team of industry veterans play a crucial role in delivering efficient and functionally accurate silicon across compute, memory management, high-speed connectivity, and other pivotal technologies


Responsibilities include:

  • Contribute to silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design
  • Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design
  • Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout
  • Work closely with the verification, DFT and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results


Requirements:

  • Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon
  • 5+ years in RTL Design/microarchitect position in industry
  • Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for chip design and related flows
  • Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities
  • Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals
  • Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off
  • Knowledge of DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off
  • Familiarity with verification, emulation platforms and methodologies is a plus
  • Hands-on experience with participation in silicon debug and bring-up is a plus


Please apply here or reach out to me at ltomaszko@acceler8talent.com to hear more.