Socionext US | Physical Design Engineer

5 days ago

san jose, United States Socionext US Full time

Physical Design Engineer – Milpitas, CA


Description

Socionext Inc. (SNI) is an innovative enterprise that designs, develops and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage and other dynamic technologies that drive today’s leading-edge applications. Socionext combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, Socionext Inc. is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities. Socionext America Inc. (SNA), a wholly owned subsidiary of SNI based in Milpitas, CA.


Socionext America is seeking a Staff Physical Design Engineer for our Milpitas, CA office. This is a hands-on technical position and will have opportunities to work on a variety of challenging designs. The position will work closely with customers, front-end, and physical design teams to ensure successful tape-outs.


Primary Responsibilities:


  • Overall design support to ASIC customers with emphasis on Front-end and Physical design
  • Perform Physical synthesis, timing feasibility analysis and SDC validation at block-level and top-level
  • Review block-level/top-level clock specifications for completeness and feasibility
  • Handle all the Physical design tasks (Floorplanning, Placement, Clocktree synthesis, Routing and Timing closure)
  • Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)


Necessary Qualifications:

· BSEE/MSEE, with 10+ years of experience. MSEE preferred

· Strong experience in Synthesis, Physical Design and STA; Experience in an SoC product development organization with tape-out experience at 28nm/16nm/7nm design nodes

· Understanding the full scope of customer’s design and support all design integration tasks

· Hands-on experience with synthesis tools like Design Compiler/Genus and physical implementation tools like ICC2/Innovus

· Strong problem-solving skills and ability to analyze and resolve timing/physical design issues is required

· Experience with power analysis and IR-drop tools (primepower/Redhawk/Voltus) and Static Timing Analysis (Primetime/Tempus)

· Experience with Physical Verification and fix PV errors in layout

· Expert handling of Verilog HDL based Netlists, Physical design libraries, Scripting (Perl/Tcl/Python) is required

· Good understanding of ASIC front-end design and working knowledge of Verilog/System Verilog

· Team player with good interpersonal and communication skills

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