ASIC/SOC Micro-Architect and RTL Design Engineer

ASIC/SOC Micro-Architect and RTL Design EngineerJoin to apply for the ASIC/SOC Micro-Architect and RTL Design Engineer role at MatXOverviewMatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies.What You’ll Do HereContribute to MatX\'s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, and full-chip designOwn entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready designPlan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards silicon milestones including design freeze and tapeoutWork closely with the verification, DFT, and physical design co-owners of the subsystem/block to achieve best-in-class performance-power-area resultsWho You AreConcept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production siliconExperience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for chip design and related flowsProduction-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalitiesExperience with testing designs and collaborating with verification teams towards performance and coverage closure goalsHands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to achieve high-quality sign-offExperience with DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and areaFamiliarity with verification, emulation platforms and methodologies is a plusHands-on experience with silicon debug and bring-up is a plusThis is a hybrid role that requires on-site work in Mountain View, CA 3 days a week (Tuesday–Thursday)CompensationThe US base salary for this full-time position is determined based on role, experience, location, job-related skills, and education and training. Career length is a guideline for compensation.0-5 years of experience - $120,000 - $200,000 + equity5-10 years of experience - $120,000 - $300,000 + equity10+ years experience - $120,000 - $400,000 + equityWhat We OfferA stake in our success with a cash/equity mixHealth & Wellness: Company-subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contributionTime To Recharge: 4 weeks paid time off, 12 company holidays, and 3 weeks remote/flexible work per yearSupport to Parents: Up to 12 weeks of paid parental leaveLearning & Development: $1,500 yearly for professional developmentTeam Connection: Team lunches, quarterly off-sites, and regular town hallsFinancial Wellbeing: 401K and/or Roth IRA with company contributionFlexible Spending Accounts: Pre-tax options for medical, dental/vision, dependent care, etc.Commute On Us: Rideshare reimbursement for commutes up to 1 hour and work-related drive-timeMatX E[x]tras: $50 per month for perksRemote Perks: Remote work support and home-office setupAs part of our commitment to diversity and inclusion, MatX is an Equal Employment Opportunity employer and will not discriminate on the basis of race, color, religion, creed, national origin, sex, gender, gender identity, gender expression, sexual orientation, age, disability, medical condition, marital/domestic partner status, military/veteran status, genetic information, or any other legally protected status. All candidates must be authorized to work in the United States and work from our Mountain View offices on Tuesday–Thursday. This position may involve access to information subject to U.S. export controls. This offer is contingent upon the applicant\'s ability to comply with U.S. export control laws. MatX does not accept unsolicited resumes from recruiters or third-party agencies. Resumes submitted are the property of MatX.Seniority levelMid-Senior levelEmployment typeFull-timeJob functionInformation TechnologyIndustriesComputer Hardware Manufacturing #J-18808-Ljbffr