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RTL Design Engineer

2 months ago

sunnyvale, United States Cambridge Terahertz Full time

Company Description

Cambridge Terahertz is a rapidly growing, venture-backed semiconductor company spun out of MIT, based in Sunnyvale, California. Recently featured in MIT News and Techcrunch, the company’s novel Terahertz imaging technology enables a wide range of impactful use cases. A true “white space” technology on the frontier of imaging technology, we are developing a silicon-based extensible imaging platform to save and improve lives across broad swaths of society. Our world-class team includes some of the best minds in RF and THz and is passionate, fast-paced and values taking on the most difficult technical challenges. We foster a creative culture that focuses on the team with strong values on self-growth and learning, and using technology to enrich lives. This is an excellent and unique opportunity for an engineer who is seeking a challenging and dynamic role in a fast-paced startup environment.


Role Description

We are seeking a skilled Verilog RTL Design Engineer to join our ASIC development team in Sunnyvale, CA on a temporary basis for a 1-2 month project (in-person preferred, remote OK). In this role, you will be responsible for designing and implementing high-performance digital logic for ASICs, with a focus on memory controllers and serial interfaces such as SPI.


Responsibilities

  • Develop and optimize RTL code in Verilog for ASIC implementation
  • Develop testbenches to validate system functionality and performance
  • Design and implement memory controllers for SRAM memory
  • Create efficient and robust serial interfaces, including SPI and other protocols
  • Perform functional and timing simulations to verify design correctness
  • Collaborate with system architects to define and refine design specifications
  • Work closely with physical design and verification teams to ensure successful tape-out
  • Participate in design reviews and contribute to documentation efforts
  • Debug and resolve design issues throughout the development process


Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
  • 5+ years of experience in RTL design using Verilog for ASIC development
  • Strong knowledge of digital design principles and computer architecture
  • Proven experience designing memory controllers (eg SRAM) for ASICs
  • Expertise in implementing serial interfaces, particularly SPI
  • Proficiency with industry-standard EDA tools for synthesis, simulation, and timing analysis
  • Strong analytical and problem-solving skills
  • Excellent communication abilities and teamwork orientation
  • Knowledge of UVM and formal verification methodologies is beneficial

The ideal candidate will have a passion for digital design, a keen eye for detail, and the ability to work effectively in a fast-paced, collaborative environment. If you are excited about pushing the boundaries of ASIC design and contributing to cutting-edge technology, we encourage you to apply.