Package Design Engineer – Principal Engineer

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > Packaging Engineering

General Summary

We are seeking a Principal Engineer / Director of Engineering to lead and develop our package design team within CHS, driving next‑generation high‑performance compute (HPC) package and system architecture for Qualcomm Datacenter business unit. This leader will own the end‑to‑end package design strategy — from concept through production — and will be responsible for building a world‑class team that delivers differentiated solutions leveraging advanced 2.5D and 3D integration technologies. The ideal candidate brings deep technical expertise in multi‑chiplet packaging, silicon interposer and bridge architecture, and high‑density interconnect design, combined with a proven track record of leading large, cross‑functional engineering organizations. The role requires strong competency in high‑speed IO system design, signal and power integrity simulation, and thermal/mechanical co‑design for advanced package substrates. The successful candidate will partner closely with silicon design, platform architecture, and manufacturing teams to define package technology roadmaps that meet aggressive performance, power, and cost targets across Qualcomm's compute portfolio. Experience navigating OSAT and foundry ecosystems, driving design‑for‑manufacturability, and influencing industry standards is highly valued. This is a senior leadership position that demands both strategic vision and hands‑on technical credibility.

Role and Responsibilities

• Provide technical and organizational leadership for the CHS Datacenter package design team; recruit, develop, mentor, and retain a high‑performing team of package architects, physical designers, and technical leads.
• Own the end‑to‑end advanced package architecture and design strategy for Datacenter and high‑performance compute (HPC) products, from early feasibility and technology selection through design release, qualification, production ramp, and sustaining support.
• Drive architecture selection and configuration optimization for advanced multi‑die packages, including 2.5D/3D integration, HBM, silicon interposers, silicon bridges, high‑density organic substrates, and other emerging chiplet integration technologies.
• Lead chip‑package‑board co‑design across silicon floorplan, die partitioning, bump maps, HBM and chiplet placement, package pinout, routing architecture, power delivery, package size, board escape, and system constraints.
• Partner with silicon design, physical design, platform architecture, SI/PI, thermal, mechanical, product engineering, manufacturing, and supply‑chain teams to balance performance, power, thermal, reliability, yield, schedule, and cost objectives.
• Guide Package/SiP physical design, layout optimization, design verification, tapeout, design reviews, and release readiness; establish clear ownership, technical checkpoints, and execution plans across the team.
• Define package‑level electrical requirements for high‑speed and high‑bandwidth interfaces, including HBM, UCIe and other die‑to‑die links, PCIe, DDR, and high‑speed SerDes; ensure package designs meet signal‑integrity and power‑integrity targets.
• Drive thermal‑mechanical co‑design and reliability risk mitigation for high‑power, large‑body packages, including warpage, stress, assembly interactions, cooling interfaces, and package‑board interactions.
• Establish and continuously improve scalable package design methodology, CAD infrastructure, automation, DRC/DFM/ERC signoff, data management, design reviews, and release processes.
• Lead technical engagement with foundries, OSATs, substrate suppliers, EDA vendors, and technology partners to define design rules, evaluate new capabilities, resolve technical issues, qualify technologies, and support production ramp and yield improvement.
• Develop package technology and capability roadmaps aligned with Qualcomm Datacenter product plans; identify technology gaps, assess technical and supply risks, and drive mitigation plans and executive‑level recommendations.
• Create a culture of technical excellence, collaboration, accountability, and innovation; coach senior engineers, develop successors and technical leads, and raise package‑design capability across the broader organization.
• Represent package engineering in program and executive reviews, clearly communicating architecture tradeoffs, technical risks, resource needs, dependencies, and closure plans.

Skills

• Proven leadership of advanced package design or package architecture teams, including hiring, mentoring, performance development, workload planning, and building technical leadership capacity.
• Deep expertise in advanced semiconductor packaging for AI, HPC, server, or networking products, including multi‑chiplet 2.