Memory System Architect

1 month ago

san jose, United States PER International Full time

CLIENT

As a top fabless semiconductor company, they power over 2 billion devices yearly, from mobile phones and home systems to automotive and IoT. Their energy-efficient SoCs are in 20% of households and nearly 1 in 3 mobile phones worldwide.


With 25+ years of innovation, they specialize in mobile tech and multimedia products like smartphones, Chromebooks, smart TVs, and Voice Assistant Devices, partnering with global brands to make smart technology accessible to all.


RESPONSIBILITIES

  • Collaborate with system architects to develop competitive and scalable memory system architectures.
  • Lead memory system design and architecture to optimize power, performance, and implementation.
  • Demonstrate a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5, etc.).
  • Design and implement customized memory systems for automotive applications, validating functionality, refining designs, and meeting performance and system requirements.
  • Ensure compliance with automotive standards and regulations, such as ISO 26262 and Automotive SPICE.
  • Work closely with the DV team to verify RTL design.
  • Assist the software team in resolving memory system-related issues.


SKILLS & EXPERIENCE

  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science or relevant subjects.
  • Strong knowledge of computer architecture, microarchitecture, and performance optimization.
  • Solid understanding of automotive standards and requirements (e.g., ISO 26262).
  • Over 10 years of relevant experience in architecture, RTL design, performance analysis, and power optimization.
  • Proven experience in designing and optimizing system-level cache for automotive applications.
  • Expertise in automotive-grade DRAM interface standards and memory technologies (e.g., DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5).
  • Familiar with system cache, memory controllers, or DDRPHY for safety and security.
  • Knowledge of ARM processor architecture and microarchitectures is a plus.
  • Familiarity with AMBA AXI, CHI, and LPDDR4/5 interfaces and protocols is an advantage.
  • Strong communication, problem-solving, debugging, and root-cause analysis skills.


INTERESTED

To apply for this opening or to find out more about our other opportunities, please contact Georgie Rose on LinkedIn or send an email to Georgie@per-international.com

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