Memory Subsystem Architect

2 weeks ago

San Diego CA United States PER International Full time

OVERVIEW


Our client, one of the largest fabless semiconductor companies globally, spans industries like mobile communications, home entertainment, connectivity, and IoT. Headquartered in Taiwan with 41 offices worldwide, they power devices ranging from smartphones to smart TVs. Their innovation and excellence have earned them a trusted reputation worldwide.


JOB SUMMARY


In this role, you will be a key member of the Memory System Design Team, collaborating closely with architecture, modelling, silicon, software, and other design teams to create a cutting-edge design. We seek highly motivated, hands-on individuals passionate about enhancing memory performance to optimize memory access behaviour in complex systems.


Key Responsibilities And Activities Include


  • Co-work with system architect to develop competitive and scalable Memory System architecture.
  • Drive Memory System architecture and designs to optimize power, performance, and implementation.
  • System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.).
  • Develop and implement tailored Memory Systems for automotive applications.
  • Validate functionality, improve design revisions, and meet performance targets as well as system requirements.
  • Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.
  • Co-work with the DV team to well verify RTL design.
  • Support software team to resolve Memory System related issues.


Education And Experience Requirements


  • Good knowledge in computer architecture, microarchitecture, and performance.
  • Good knowledge of the automotive requirements and standards (e.g., ISO26262).
  • 10+ years or relevant design experience and knowledge in architecture, RTL design, performance analysis and power optimization.
  • Experience in designing and optimizing system-level cache for automotive applications.
  • Experience with automotive-grade DRAM interface standards and memory technologies such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.
  • Familiarity with system cache, memory controller or DDRPHY for safety, and security.
  • Familiarity with the architecture and the micro-architectures of recent ARM processors is a plus.
  • Familiarity with AMBA AXI, CHI and LPDDR4/5 interfaces/protocols is a plus.
  • Good communication, problem-solving, root causing and debugging skills.


INTERESTED?


We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Jacqui Grimwood at PER Recruitment or send your CV to jacqui.g@per-international.com

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