ASIC/ FPGA Design Verification Engineer

3 weeks ago


El Segundo, United States Spectraforce Technologies Full time
Title: ASIC/ FPGA Design Verification Engineer
Location: El Segundo, CA
Duration: 6 Months

Required Skills:

* 5+ years of experience
* 1-2 years of UVM tool
* Cadence Xcelium verification tool

Job Description:
Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.

Education: Must have min Bachelor's in Engineering
Additional Details: Must have min 5 years of experience. UVM experience is important and required.

Successful completion of training is a contingency for this assignment - OJT or formal classroom training.

Notice to California Applicants: SPECTRAFORCE is committed to complying with the California Privacy Rights Act ("CPRA") effective January 1, 2023; and all data privacy laws in the jurisdictions in which it recruits and hires employees. A Notice to California Job Applicants Regarding the Collection of Personal Information can be located on our website. Applicants with disabilities may access this notice in an alternative format by contacting NAHR@spectraforce.com.


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