Senior Mask Layout Engineer
1 month ago
Location: San Jose, CA (Must be on-site)
LOA: 6-12 months
Skills: Analog Layout 7nm/5nm FInFET, TSMC, RF, High Speed, PLL, Serdes
Location: San Jose, CA
Analog and Mixed-Signal Layout Engineer
Job Description
The candidate should be able work independently on block level and IP level Analog layout design, coordinating with the circuit designer and the rest of the layout team. The candidate will need to be able to work with both design engineers and mask design engineers in remote locations, and thus the ability to plan and efficiently use email and Webex to review critical aspects of the layout work is essential to this role.
The candidate should have experience with the layout of high-frequency analog and high-speed custom digital circuits in which parasitic minimization is critical.
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