System-on-Chip Design Engineer
3 weeks ago
Job Title: ASIC/RTL Design Engineer
Primary Skills : SOC , System Verilog , ASIC engineers like Synopsis , PERL, Python or Tcl
Location: San Jose, CA
Duration : 12+ Months
Job Description:
Title: ASIC/RTL Design Engineer
100% onsite (4 days a week in office, Friday optional)
Duration: 12+ months contract
Top 3 skills: Good understanding of System Verilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Synopsis, etc. - scripting is nice to have
KEY RESPONSIBILITIES:
• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and successful tape out.
• Design and implement logic functions that enable efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
• Implement automation to increase design team efficiency.
PREFERRED EXPERIENCE:
• Must have proven track record of ASIC design on several production tape-outs.
• Experience in Designing RTL block for an SOC.
• Experience in integrating ASIC IP into an SOC.
• Experience with Arm architecture and APB, AXI, CHI protocols.
• Experience with synthesis, static timing analysis & optimizations.
• Experience with design involving Interconnects.
• Experience writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl
• Ability to develop clear and concise engineering documentation.
• Experience in Power-saving techniques.
• Ability to organize and present complex technical information.
• Strong verbal and written communication skills
Thanks & Regards
Shaik Sadeq
Infobahn Soft world Inc.
Email: Sadeq@infobahnsw.com
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