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Design validation engineer
2 months ago
Job Description:
We are seeking a highly skilled and experienced Design Validation Engineer specializing in Formal Design Verification to join our dynamic engineering team. The ideal candidate will have over 10 years of experience in digital verification and a strong proficiency in UVM (Universal Verification Methodology). In this role, you will play a crucial part in ensuring the accuracy and reliability of our digital designs through formal verification methodologies.
Key Responsibilities:
- Lead the formal verification of digital designs, ensuring they meet the highest standards of accuracy and reliability. Utilize formal methods to verify design properties and identify potential issues early in the design cycle.
- Execute and manage comprehensive digital verification processes, including creating and maintaining verification plans, developing testbenches, and analyzing coverage metrics.
- expertise in UVM to develop and maintain verification environments. Create reusable verification components, stimulus generators, and checkers within the UVM framework.
- Participate in design reviews and provide feedback on verification strategies, test plans, and design methodologies. Work closely with design engineers to understand the requirements and ensure comprehensive verification coverage.
- Design and implement testbenches to simulate and validate digital designs. Ensure the accuracy and completeness of testbenches, enabling the detection of functional and performance issues.
- Identify, analyze, and resolve issues detected during the verification process. Work closely with the design team to debug and resolve issues, ensuring timely delivery of verified designs.
- Prepare detailed reports on verification progress, results, and any identified issues. Maintain accurate and up-to-date documentation of verification processes and methodologies.
Qualifications:
- Experience: 10+ years of experience in digital verification, with a proven track record in formal design verification.
- Technical Proficiency: Deep understanding of UVM and its application in digital design verification. Experience with formal verification tools and methodologies.
Educational Background:
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Skills: Strong problem-solving skills, attention to detail, and the ability to work independently as well as in a team environment. Excellent communication skills, with the ability to present complex technical information clearly.
