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Senior FPGA Engineer

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Santa Clara, United States Data Capital Incorporation Full time

About the RoleThe FPGA Verification Engineer will be responsible for ensuring the quality and reliability of our FPGA designs through rigorous verification processes. This role requires a strong background in SystemVerilog and UVM, along with hands-on experience in verification methodologies.ResponsibilitiesFPGAVerification ExpStrong SystemVerilog Coding (Universal Verification Methodology) - UVM4+ years of FPGA verification experienceStrong SystemVerilog programming skillsHands-on experience with UVM (Universal Verification Methodology)Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)Experience with code and functional coverage analysisProficient in debugging and problem-solvingScripting experience in Python or PerlKnowledge of Verilog and/or VHDL