FPGA Verification Engineer

3 days ago

Santa Clara, United States Compunnel, Inc. Full time

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our team.
This role is responsible for verifying complex FPGA designs to ensure functionality, performance, and reliability.
The ideal candidate will work closely with design engineers to develop and execute verification plans, debug issues, and contribute to the overall quality of deliverables.
Key Responsibilities Develop and execute comprehensive verification plans for FPGA designs.
Create and maintain test benches using industry-standard methodologies (e.g., UVM, SystemVerilog).
Write and debug test cases to verify functionality, performance, and edge cases.
Perform code coverage and functional coverage analysis.
Collaborate with design engineers to identify and resolve issues.
Document verification results and provide clear reports.
Participate in design reviews and contribute to verification strategy.
Stay current with verification methodologies and tools.
Automate design tasks and write scripts to generate reports.
Contribute to innovation efforts aimed at reducing design cycle time and cost.
Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in FPGA verification.
Strong understanding of FPGA design principles and architectures.
Proficiency in SystemVerilog and UVM.
Experience with verification tools such as QuestaSim, Synopsys VCS.
Knowledge of code and functional coverage analysis.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).
Strong debugging and problem-solving skills.
Excellent communication and collaboration abilities.
Preferred Qualifications Experience with EDA tools from Cadence, Synopsys, or Mentor.
Understanding of bus protocols (e.g., AHB, AXI, PCIe, USB, Ethernet, SPI, I2C).
Exposure to physical design, DFT, STA, and analog layout.
Knowledge of CMOS, FinFET, FDSOI technologies (28nm and below).
Experience in automation and scripting for design efficiency.
Participation in technical forums, white papers, or patent filings.

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