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Senior Design Verification Engineer
4 months ago
Qualifications
Proven track record of success in verification strategy development and execution for large SoC and signoff with coverage metrics
Hands-on knowledge of UVM methodology, System Verilog, C/C++
Implement directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, and multi-CPU environments
In-depth understanding of networking standards, bus protocols, high-speed serial link protocols
Experience with CPU instruction set testing and cache coherent system testing
Knowledge of verification IP and functional coverage techniques
Experience with gate-level simulations of delay annotated netlists
Exposure to FPGA emulation and lab validation.
Project planning and execution and performing test strategy tradeoffs to achieve coverage and schedule targets
Strong leadership and experience building world-class verification teams.
