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[CONTRACT] UVM Verification Engineer

3 months ago

Carlsbad, United States Microtech Global Ltd Full time

Job Description Job Title:

UVM Verification Engineer

Job Type:

Contract

Location:

France/Remote

Duration:

6 months' initial

Start:

ASAP

Job Responsibilities

Define and implement verification methodologies

Elaborate detailed verification plan corresponding to the circuit specifications

Write block and top-level self-checking test benches

Implement regression tests on RTL and gate-level netlists

Support the Analog design team in mixed-signal simulations

Participate in the evaluation of the fabricated ASIC in our measurement lab

Work in a team to successfully design a state-of-the-art ASIC

Participate in design reviews

Write documentation in accordance with company QA policy

Qualification and Experience

Qualifications:

Hands-on experience in digital IC verification

Background in digital electronic and signal processing

Solid knowledge of digital hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)

Knowledge of System Verilog

Experience with UVM methodology is a plus

Experience in formal verification is a plus

Experience in gate-level simulation is a plus

Good analytical and problem-solving skills

Previous experience in verification of digital functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus

Previous experience with Cadence or Synopsys RTL design flow is a plus

Previous experience with FPGA is a plus

Team player with a critical attitude and sense of initiative

Fluent communication in English (oral and written)

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