PCIe, CXL, DDR, or Ethernet Design Verification Engineers
3 weeks ago
We are looking for Principal Design Verification Engineers with proven experience working on industry-standard protocols such as PCIe/CXL/DDR/Ethernet. Using your coding and protocol expertise, you will contribute to the functional verification of the designs, from coming up with block-level and system-level verification plans to writing test sequences, test execution, collecting, and closing coverage.
Basic qualifications
- Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE is required, and a Master's degree is preferred.
- ≥10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
- Knowledge of industry-standard simulators, revision control systems, and regression systems
- Entrepreneurial, open-minded behavior, and can-do attitude. Think and act fast with the customer in mind
- Authorized to work in the US and start immediately.
Required Experience
- Experience with interpreting PCIe/CXL standard protocol specifications to come up with a verification plan and execute them in simulation environments.
- Must be able to work independently to develop test plans and related test sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
- Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties, and analyzing coverage data.
- Must have prior experience using Verification IPs from 3rd party vendors for PCIe/CXL (with a focus on Gen3 or above)
- Develop VIP abstraction layers for sequences to simplify and scale verification deployments.
- Currently based locally or open to relocation.
Preferred Experience
- Physical Layer, Link Layer, and Transaction Layer verification expertise in PCIe /CXL protocol
- Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
- Experience in analyzing performance metrics of CXL/PCIe
- Experience in system-level verification for PCIe/CXL
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