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Senior Digital Design Engineer

3 months ago

San Jose, United States ALOIS Solutions Full time

Title: Digital Design Engineer, PCIe

Location: San Jose, CA


Job Description:


  • Define block level micro-architecture and write design specification
  • RTL implementation of the specification while meeting power, area, timing constraints
  • Work with Verification team to verify functionality
  • Work with Backend team to go through ASIC flow to tape-out success
  • Work with Firmware teams to develop APIs and help silicon bring up
  • Post-silicon validation and debug



Minimal Qualifications:



  • Master’s degree in Electrical Engineering or related field
  • 3 years of industrial experience in ASIC Design
  • Experience in micro-architecture and RTL design of complicated blocks
  • Proficient in RTL design using HDL
  • Familiar with design and verification tools (VCS, Verdi, DC, etc.)
  • Hands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug
  • Proficient scripting language in one of: Python, TCL, Shell, Perl
  • Self-motivated team worker



Preferred Qualifications:



  • Hands on design experience in PCIe logical / link / transaction layers.
  • Knowledge of PCIe / CXL Protocol Stacks, especially latest Generations
  • Experiences in SerDes architectures
  • Experiences in Digital Signal Processing
  • Good debugging and problem-solving skills