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Senior RTL Design Engineer

5 months ago

San Jose, United States Trilyon, Inc. Full time

Trilyon Inc. is looking for a Senior RTL Design Engineer for its direct client. If you have the skills and experience mentioned below, we would love to discuss it with you.


Location: Onsite San Jose, CA

Duration: 12 Plus Months


JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debugging. Read and comprehend the System on Chip level architectural specification. Write microarchitecture specifications for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.


EDUCATION: Bachelor's or Master's in Computer Engineering.


KEY RESPONSIBILITIES:

  • Perform RTL design of digital components in Verilog/systemverilog.
  • Analyze/fix Lint and CDC errors of the components.
  • Guarantee quality/timely deliverables meeting the project’s schedule.
  • Help to improve/automate the design process.


PREFERRED EXPERIENCE:

  • Knowledge of RISK-V processor integration Express
  • Multi-clock domain designs.
  • Design constraints for synthesis and static timing analysis.
  • Knowledge of AXI/AMBA protocol
  • Knowledge of front-end RTL design tools and methodologies.
  • Knowledge of scripting languages like Perl, tcl, or shell