Silicon Verification Engineer

5 days ago

Mountain View, United States Randstad Full time

Description:

Typical Day in the Role

• Purpose of the Team: The purpose of this team is: The team are group of verification engineers. They test out designs before it becomes silicon. They are looking for someone to do pre-silicon verification work.


Compelling Story & Candidate Value Proposition

• What makes this role interesting? - This role provides the opportunity to: This type of verification can span simulation and emulation, is not done by the same team in most silicon companies. Even in our company it is not in every team. Only a few teams does testing of this kind, multiple platforms based testing, its very unique.


Candidate Requirements

• Years of Experience Required: 7+ overall years of experience in the field.

• Degrees or certifications required: BA in electrical / computer engineering - degree is required to be eligible for this role.

• Disqualifiers: Candidates with missing requirements & running tests but not taking tests from start to finish will not be eligible for the role.


• Best vs. Average: The ideal resume would contain UVM and System Verilog based verification experience (minimum 7 years of this).

• Performance Indicators: Performance will be assessed based on work assigned that can be completed, then if the person is consistently not completing work with quality of asking too many questions that take away from the team. After 1 month of coaching and prepping, and the person is not naturally weaning then we will have to reconsider.


Top 3 Hard Skills Required + Years of Experience

1. Minimum 7 years experience with UVM/System Verilog

2. Minimum 7 years experience with scripting language

3. Minimum 7 years experience with write and debug tests in UVM


Hard Skills Assessments

• Expected Dates that Hard Skills Assessments will be scheduled: ASAP

• Hard Skills Assessment Process: The assessment process will include : phone screen , then 3-4 hour panel.

• Required Candidate Preparation: Candidates should have coding questions prepared prior to the assessment:


Must be able to implement a UVM/System Verilog test bench from scratch, create agents, scoreboards, checks, assertions, cover-points.

Must know at least one scripting language (a plus if it is python).

Must be able to write and debug tests in UVM, using Verdi source code level debugger.

Bachelors in Computer Science, Electrical/Electronics + 7 years verification experience using UVM/SystemVerilog Methodology OR

Masters in Computer Science, Electrical/Electronics + 5 years verification experience using UVM/SystemVerilog Methodology


(W2 opportunity)

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