Fellow Software Architect Static Timing Analysis Optimization Lead
1 week ago
We are dedicated to enriching our industry, communities, and the world through innovative AMD technology. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded.
The Role:
We are seeking a Fellow Software Architect to lead the specification and development of FPGA Static Timing Analysis (STA) features for the next generation STA tools.
You will provide technical leadership and architectural guidance to advance STA capabilities on current and future devices, focusing on performance, accuracy, and quality.
Key Responsibilities:
Design, implement, and test FPGA STA capabilities, suitable for placement, optimization, routing, and signoff timing
Evaluate and provide STA support for new FPGA architectures
Collaborate with Tech Marketing and Applications Engineering to understand customer needs and drive required STA support
Preferred Experience:
Extensive experience in architecting and implementing high-performance, high-capacity STA engines
Comprehensive understanding of multi-mode/multi-corner and variation-aware STA
Expertise in state-of-the-art EDA algorithms
Detailed knowledge of SDC timing constraints
Knowledge of Digital Design and FPGA implementation
Proficiency in C++ programming
Solid foundation in software engineering, with strong analytical and debugging skills
Excellent verbal communication and writing skills, and executive-level presentation skills
Experience with TCL, Python, Perl, or other scripting languages
Comfortable communicating with all levels of the organization, especially executive-level personnel
Academic Credentials:
Master's degree or Ph.D. in Electrical Engineering or Computer Science or related equivalent
Location:
Longmont, CO, or San Jose, CA
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