Principal ASIC Timing Engineer
7 days ago
Principal ASIC Timing Engineer
About the Opportunity:
We are seeking an experienced ASIC Timing Engineer with a strong focus on frontend timing to join a cutting-edge hardware startup developing transformative solutions for next-generation transformer architectures. This company is pioneering advancements in hardware performance and efficiency for machine learning workloads.
As an ASIC Timing Engineer, you will play a pivotal role in ensuring the success of complex chip designs by driving timing analysis and closure at the frontend stages. This is an exceptional opportunity to work on innovative hardware solutions in a collaborative and fast-paced environment.
Key Responsibilities:
- Own and drive timing analysis and closure for frontend design stages, including pre-synthesis and post-synthesis phases.
- Collaborate closely with RTL designers to identify and resolve timing issues at the architectural and block levels.
- Develop and refine timing constraints (SDC) to ensure accurate and efficient synthesis and STA.
- Perform static timing analysis (STA) using industry-standard tools and methodologies, focusing on critical path identification and optimization.
- Work with cross-functional teams to debug and address setup, hold, and clock domain crossing (CDC) issues.
- Support backend timing closure by providing clean handoffs with well-defined constraints and timing signoff reports.
- Automate timing workflows and scripts to improve efficiency and consistency across projects.
- Stay updated on timing methodologies and contribute to the development of best practices and flows.
Qualifications:
- 3+ years in ASIC timing analysis and closure, with a focus on frontend stages.
- Strong expertise in static timing analysis (STA) tools such as Synopsys PrimeTime, Cadence Tempus, or similar.
- Deep understanding of timing constraints (SDC) creation and validation.
- Solid knowledge of RTL design and the ability to collaborate effectively with designers to optimize timing.
- Proven track record of resolving complex timing issues, including setup, hold, and CDC challenges.
- Proficiency in scripting languages such as Python, Tcl, or Perl for automation of timing workflows.
- Strong analytical skills and the ability to debug and resolve timing-related issues.
- Excellent communication and teamwork skills to work effectively with cross-disciplinary teams.
Preferred Qualifications:
- Experience with high-performance computing architectures or AI accelerators.
- Familiarity with advanced process nodes (e.g., 5nm, 3nm) and associated timing challenges.
- Knowledge of power-aware timing analysis and multi-corner, multi-mode (MCMM) optimizations.
- Background in clocking architectures and low-power design techniques.
Why Join Us?
- Work on groundbreaking hardware technologies designed to accelerate AI and machine learning applications.
- Be part of a dynamic startup environment with significant opportunities for impact and growth.
- Competitive compensation package, including benefits and equity.
- Collaborate with a world-class team and work on advanced technologies shaping the future of hardware.
How to Apply:
If you’re passionate about timing engineering and excited to contribute to cutting-edge hardware innovation, we’d love to hear from you. Please apply here or reach out to Luke at ltomaszko@acceler8talent.com to hear more.
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cupertino, United States Acceler8 Talent Full timePrincipal ASIC Timing Engineer About the Opportunity:We are seeking an experienced ASIC Timing Engineer with a strong focus on frontend timing to join a cutting-edge hardware startup developing transformative solutions for next-generation transformer architectures. This company is pioneering advancements in hardware performance and efficiency for machine...
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