Digital IC Design Principal Engineer
4 months ago
*Date Posted:* 2024-06-11*Country:* United States of America*Location:* CA602: Goleta (RVS) Bldg B01 6825 Cortona Drive Building B01, Goleta, CA, 93117 USA*Position Role Type:* HybridAt Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world. Raytheon Vision Systems is seeking to hire a talented digital design engineer to join our strong team. In this position, you will be part of a talented team designing next-generation digital visible and infrared image sensors. A successful candidate will excel at collaborating in a fast-paced multidisciplinary team environment working to develop cutting-edge image sensor products. As part of this team, you will be participating in mixed-signal ASIC/ROIC development activities with cross-functional teams, including chip architecture, specification, design, verification, validation, fabrication, packaging, debugging, test development, failure analysis, and documentation. You will work to develop new digital block level microarchitectures, plan work breakdown structures and tasking, design digital logic blocks using Verilog and SystemVerilog HDL and utilize in-house digital IPs to extend functionality and/or to be compatible with new requirements for design reuse. What You Will Do:
- You will work with other team members to design and implement innovative Readout Integrated Circuits for cutting-edge imaging systems, including digital blocks (1k – 1M gates) in a variety of CMOS nodes (from 180nm to 28nm).
- You will collaborate in cross-functional integrated product development teams to deliver on customer requirements with consideration for efficiencies in strategic investment, cost, schedule, and process adherence.
- You will train and guide junior engineers.
- BS, Electrical Engineering with 8 years of prior relevant experience
- MS, Electrical Engineering with 6 years of prior relevant experience
- PhD, Electrical Engineering with 4 years of prior relevant experience
- Experience with full Digital Design Flow that includes writing RTL using Verilog & SystemVerilog, constructing testbenches to perform RTL simulation & verification, performing Synthesis, Static Timing Analysis, Place-and-Route, DFT (with use of scan chains), and Logical Equivalence Check.
- Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus, TCL scripting and Lint tools.
- U.S. citizenship is required, as only U.S. citizens are authorized to access the financial management system due to government contractual requirements.
- Experience with ROIC architecture, design concepts, operational control and timing.
- Experience writing behavioral models for digital circuits and analog/mixed signal interfaces and circuits.
- Experience with Conformal
- Experience with a Digital-on-Top mixed-signal design flow including utilization of Innovus for final chip construction.
- Advanced degree
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