Quality Floor Lead

1 month ago

San Jose CA, United States Cisco Full time

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

You'll be joining our Cisco Silicon One team which is the center of Cisco’s SW and ASIC design, and will be part of our group driving our game changing next generation network devices - Cisco Silicon One. Our unique team works in a startup atmosphere inside a stable and leading corporate.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come You'll be joining our Physical Design team at Cisco Silicon One group, which is responsible for the entire development process of RTL to GDS, leading development of high quality VLSI designs.
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design


You are a Design Engineer with 12+ years of related work experience with a broad mix of technologies


Bachelor’s degree in Electrical Engineering or equivalent similar experience.
~12+ years experience in physical design
~ Understanding of RTL2GDSII flow and design tapeouts in 16nm/7nnm/5nm or below process technologies.
~ Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
~ Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in Block-level and Full-chip floor-planning and power grid planning.
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
Experience with Python, TCL, Perl programming.

#We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).

Because without diversity of thought and a dedication to equality for all, there is no moving forward.
Don’t care. Tattoos? Passion for technology and world changing?

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