High-Speed Interconnect Senior Validation Engineer

High-Speed Interconnect Senior Validation Engineer Intel Corporation | Apply | Full-time | Hillsboro | Advanced (5-10 yrs)

Job Description

We are seeking a High-Speed Interconnect Validation Engineer to lead end-to-end validation of next-generation data center and AI platform interconnects—including PCIe, CXL, and UALink—spanning node, rack, and large-scale cluster environments. This role is heavily focused on ensuring interoperability, performance, reliability, and standards compliance of high-speed I/O fabrics that power modern AI and HPC systems. The ideal candidate has deep technical knowledge of high-speed protocols, strong platform-level debug skills, and a passion for validating complex systems at scale.

Key Responsibilities

Own validation strategy, test planning, and execution for PCIe, CXL, and UALink across silicon, platform, rack, and cluster configurations. Develop comprehensive validation coverage for link training, error handling, fabric scaling, congestion, performance, and protocol compliance. Perform bring-up and debug of high-speed I/O subsystems using protocol analyzers, exercisers, and signal measurement tools. Validate interconnect behavior under AI/ML workloads, stress conditions, and multi-node traffic patterns. Drive interoperability testing across GPUs, accelerators, switches, storage, and memory devices from diverse ecosystem partners. Collaborate with silicon design, board design, firmware, and software teams to resolve complex cross-layer issues. Build automation, diagnostics, and scaling frameworks to validate fabrics at rack-level and multi-rack cluster scale. Analyze performance metrics, identify bottlenecks, and recommend architectural or firmware tuning for optimal interconnect efficiency. Influence next-generation high-speed I/O roadmap by providing data-driven insights from validation cycles. Engage with hyperscalers, OEMs/ODMs, and industry partners to ensure end-to-end readiness for deployment. What You'll Gain Opportunity to validate the fastest and most advanced interconnects powering modern AI systems. Hands-on experience from silicon bring-up to rack-scale cluster validation. Influence the architecture and deployment readiness of next-generation data center fabrics. Qualifications

Minimum Qualifications

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience 8+ years of experience in SoC and Validation Hands‑on experience validating high‑speed I/O standards such as PCIe Gen4/5/6, CXL 2.0/3.0, or UALink. Solid understanding of protocol layers, link training, flow control, and fabric management. Experience with high‑speed debug tools (protocol analyzers, exercisers, oscilloscopes, BERTs). Strong system‑level debug skills across hardware, firmware, BIOS, OS, and drivers. Familiarity with data center or AI platform architecture.

Preferred Qualifications

Experience validating large-scale AI clusters, GPU/accelerator fabrics, or coherent memory pooling. Deep knowledge of CXL switching, memory expansion, and coherency models. Experience with SI/PI fundamentals and their impact on validation outcomes. Familiarity with automation frameworks (Python, Jenkins, etc.) for multi‑node testing. Prior collaboration with open standards bodies or hyperscale customers. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, Oregon, Hillsboro Additional Locations US, California, Santa Clara Business Group At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For interns, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: Annual Salary Range for jobs which could be performed in the US: $214,730.00 USD - $303,140.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr