Senior Microelectronics Process Engineer

Job ID: TAP00092 Position: Senior Microelectronics Process Engineer Location: US – MD, Fort Meade (or surrounding area) Category: Hardware Clearance Requirement: Active TS/SCI w/ full scope polygraph Education Requirement: BS in Mechanical, Manufacturing, Chemical, Materials Science, or Electrical Engineering (or related technical field) Experience Requirement: 15 Years TAP is seeking to hire a Senior Microelectronics Process Engineer to join our team If you are a highly motivated engineer who enjoys a challenging and dynamic environment where your contributions are both critical and valued, this company will provide you the tools and opportunity to thrive. The Senior Microelectronics Process Engineer will lead and support microelectronics manufacturing projects at all levels of integration: die/wafer, component level packaging, multi-chip module (MCM), printed circuit board (PCB), and system level packaging. Required Qualifications Active TS/SCI w/ full scope polygraph BS in Mechanical, Manufacturing, Chemical, Materials Science, or Electrical Engineering (or related technical field) 15+ Years of overall engineering experience 11+ years of experience working in electronics hardware manufacturing Experience fabricating, assembling and qualifying 1st article engineering prototypes Experience with hands‑on electronics fabrication (i.e. soldering) Experience designing, validating and optimizing processes leveraged in the fabrication of microelectronics hardware Experience developing, iterating, troubleshooting, documenting, and communicating manufacturing processes within a production environment Experience interpreting test and failure analysis results, and providing recommendations or alternatives Experience researching, evaluating, selecting and recommending electronic materials (i.e. underfill, overmold, die attach, adhesives, thermal interface materials, etc.) Experience with development, capture and flow‑down of technical requirements Experience developing and executing test plans and procedures Technical writing, communication, and interpersonal skills Desired Qualifications MS in Mechanical, Manufacturing, Chemical, Materials Science, or Electrical Engineering (or related technical field) Familiarity with the following packaging and interconnect technologies/processes: Chip Scale Packaging, BGA Packaging, Multi‑Chip Module Packaging, High Density Interconnect, Stacked Die Interconnect, Flip Chip Interconnect, Wirebonding, Redistribution Layers (RDL), Fan‑Out‑Wafer‑Level Packaging (FOWLP), SMT Assembly, Thermal Compression Bonding, Gold Stud Bump Bonding, Low Stand‑Off Underfilling, Wafer‑to‑Wafer and Die‑to‑Wafer Bonding Experience programming and operating automated production equipment (i.e. wafer thin/backgrind, wafer dice, die pick and place, wirebond, SMT pick and place, SMT reflow, Xray Inspection, Automated Optical Inspection, etc.) This position is contingent upon the successful completion of security processing and favorable acceptance onto the program by the Customer. Clearance Requirement: This position requires the ability to obtain and maintain a Top Secret/SCI security clearance, based on current background investigation (SBI), as well as the favorable completion of full scope polygraph. Clearance and polygraph processing will be completed by the U.S. Government. Factors considered for a U.S. Government Security Clearance include, but are not limited to: U.S. Citizenship Favorable Criminal History Check Education Verification Abuse/Illegal Drug Use Credit Check Subject Interview By submitting your resume for this position, you understand and agree that TAP Engineering may share your resume, as well as any other related personal information or documentation you provide, with its subsidiaries and affiliated companies for the purpose of considering you for other available positions. TAP Engineering is an Equal Opportunity Employer and applicants receive lawful consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status. #J-18808-Ljbffr