Interconnect Architect

3 weeks ago

Austin, United States Oho Group Ltd Full time

Interconnect Architect


Hiring for an exciting RISC-V start-up who have the objective to revolutionize the industry by developing computing platforms through hardware/software co-design, leveraging cutting-edge technologies. As a fabric architect, your role entails defining the internal interconnect architecture specification and determining its performance, power, and area requirements. This encompasses both coherent and non-coherent interconnects, as well as chiplet-to-chiplet connections. You will collaborate closely with members of the Silicon team (e.g., RTL/microarchitecture, DV, PD, Perf, DFT), as well as engage with industry consortia such as UCIe.


Interconnect Architect Requirements:

  • Comprehensive understanding of large-scale on-chip fabric or on-chip interconnect architecture.
  • Familiarity with various on-chip network protocols such as AMBA, AXI, CHI, ACE, Tilelink, or APB.
  • Knowledgeable about cache-coherent memory systems and interconnect.
  • Understanding of different on-chip network topologies like ring, mesh, xbar, etc.
  • Proficiency in SystemVerilog or Verilog, C or C++, and scripting languages like Python.
  • Experience working with functional and performance simulators.
  • Understanding of logic design principles, including timing and power implications.
  • Knowledge of low-power architecture techniques.
  • Awareness of high-performance techniques and trade-offs in fabric architecture.


Interconnect Architect Responsibilities:

  • Contribute to architecture development and specification, spanning from early high-level architectural exploration to providing microarchitectural direction and crafting detailed specifications.
  • Design coherent and non-coherent interconnects within the chip, considering coherency protocols, directory structures, bandwidth, and latency targets.
  • Develop, assess, and refine architecture to meet power, performance, area, and timing objectives.
  • Assist in creating and reviewing validation plans for both functionality and performance.
  • PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area.

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