Silicon Design Engineer
3 weeks ago
We're looking for a passionate RTL and Firmware Design Engineer to join our team Be part of the creation and development of industry-leading Memory PHYs and interface IPs. You'll collaborate with experts across disciplines (RTL, FW, circuit, architecture) to define, design, and deliver cutting-edge Memory I/O solutions.
This contract will be for 12 months.
Responsibilities:
● Design, develop, and verify high-speed LPDDR & DDR IPs using RTL & Firmware
● Collaborate across teams (RTL, FW, Circuit, Architecture) to deliver cutting-edge Memory Interface IPs
● Lead new IO design creation and methodology enhancements
● Handle all stages of PHY Digital Architecture development (pathfinding, coding, verification, implementation)
● Partner with Analog & System architects on PHY link layer design & verification
● Perform digital design, RTL coding, timing synthesis, and drive physical implementation
● Understand new features, estimate test time, and build unit tests
● Debug design failures, collaborate with DV & firmware engineers to resolve issues
You're a great fit if you:
● Have 5+ years of digital design engineering experience
● Are a team player with excellent communication skills (across sites & time zones)
● Enjoy problem-solving and possess a strong learning mindset
● Proficiency in debugging firmware & RTL code using simulation tools
● Experience with UVM testbenches, Verilog, System Verilog, C, C++, and scripting languages (Python, Perl, TCL)
● Strong understanding of computer architecture, clocking, synchronization, and CDC methodology
● Experience with SERDES, DDR, Memory Controllers, or MAC Designs (a plus)
Bonus points for:
● Mixed-signal RTL experience
● Leadership or mentorship experience
Minimum Qualifications:
● Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
NOTE: Hybrid work model: 3 days a week in the office
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