Job TitleIntern

SLAC National Accelerator Laboratory seeks an Application Specific Integrated Circuit (ASIC) design engineer intern within the Integrated Circuits Department of the Instrumentation Division of the Technology Innovation Directorate. The IC department develops state-of-the-art, low-noise and low-power front-end Application Specific Integrated Circuits (ASICs) to support experiments in several fields of science, such as: ultra-fast X-ray photon science, high energy physics, quantum information science, medical imaging, biomedicine, space applications, and others. Several projects are carried out in collaboration with major research facilities in the world (CERN, NASA, LCLS) and other US government agencies and universities. Moreover, the IC department develops innovative IP solutions in collaboration with industrial partners.

The department is seeking to strengthen its capabilities in analog/mixed signal design to implement the next generation system-on-chip (SoC) ASICs. As mixed signal designer you will be using the 28nm CMOS technology to apply novel circuit design techniques for a blue-skies R&D project.

Members of our team are encouraged to work in a variety of areas, supporting multiple diverse designs in a dynamic, energetic environment which values work life balance and comes with all of the benefits of being an employee of Stanford University.

The work will include science, engineering concept development and hands-on work with VLSI CAD design tools. SLAC has broad engineering and technical support, but there will be a need for a wide range of work ranging from concept development to laboratory performance testing, to electronics and software development. This position requires exceptional adaptability in doing whatever is needed to ensure the successful realization of projects. This work involves solving problems no one has ever solved before. There will be lots of opportunities for technical discussions, but ultimately the individual in this role will have responsibility for finding the solutions.

Note: This is an hourly, non-benefits eligible temporary-nonexempt, internship position (work at 50% full-time equivalent or more), not to exceed 980 hours in six consecutive months. Eligible applicants must be at least 18 years of age, currently enrolled in an educational program or recently graduated, and have US work authorization.

Core responsibilities:

As an ASIC design intern, you will be involved in the design and integration of advanced and complex ASICs through the following assignments:

Define key specifications of analog and digital circuitry. Behavioral modeling to validate system architectures. Design of ultra-low-noise, low-power machine learning/Ising macro. Circuit design techniques for signal conditioning, reliability, and testability. Design optimization for area and power consumption. Floor planning, layout design and physical verification of active circuits. Top-level simulations to validate ASIC integration. Document design towards formal design reviews. Coordination of PCB design for chip characterization. Hands-on in lab for chip characterization and testing plans for validation.

Cross-functional responsibilities:

Engage and collaborate with SLAC cross-functional teams, including scientists and electronics engineers developing FPGAs, PCB, DAQ systems, semiconductor, and quantum sensor devices. Engage and collaborate with other national labs, research institutions and high-tech companies.

Minimum requirements:

Master’s degree or equivalent relevant experience in the field of electronics engineering or related research fields. Proficient with IC design flow and CAD tools for schematic entry, simulation, and layout design, including physical verification and top-level integration. Working experience with verification techniques of mixed-signal circuits. Working knowledge of machine learning and CMOS-based Ising machine Experience designing one or more of the following categories: machine learning accelerator, in-memory/near-memory compute macro, and CMOS-based Ising machine. Experience with version control for both analog and digital circuits. Excellent writing skills to keep track of design documentation. Strong team player. Ability to carry out responsibilities proactively. Excellent analytical thinking skills. Ability to adapt and work well in a R&D team. Good communications skills.

Preferred Qualifications:

Experience in designing memory circuits for domain specific accelerators (SRAM, EDRAM, DRAM, etc). Previous working experience in a research institution (University, US National Laboratories, CERN, NASA, etc.) Experience designing and simulating in advanced CMOS technologies (below 65nm). Experience in the lab for chip characterization, debugging, data analysis and validation. Hands-on experience with electronic instrumentation such as signal generators, spectrum analyzers, oscilloscopes, etc.

SLAC Employee Competencies:

Effective Decisions: Uses job knowledge and solid judgment to make quality decisions in a timely manner. Self-Development: Pursues a variety of venues and opportunities to continue learning and developing. Dependability: Can be counted on to deliver results with a sense of personal responsibility for expected outcomes. Initiative: Pursues work and interactions proactively with optimism, positive energy, and motivation to move things forward. Adaptability: Flexes as needed when change occurs, maintains an open outlook while adjusting and accommodating changes. Communication: Ensures effective information flow to various audiences and creates and delivers clear, appropriate written, spoken, presented messages. Relationships: Builds relationships to foster trust, collaboration, and a positive climate to achieve common goals.

Physical requirements and working conditions:

Consistent with its obligations under the law, the University will provide reasonable accommodation to any employee with a disability who requires accommodation to perform the essential functions of the job.

WORK STANDARDS:

Interpersonal Skills: Demonstrates the ability to work well with Stanford colleagues and clients and with external organizations. Promote Culture of Safety: Demonstrates commitment to personal responsibility and value for environment, safety and security; communicates related concerns; uses and promotes safe behaviors based on training and lessons learned. Meets the applicable roles and responsibilities as described in the ESH Manual, Chapter 1—General Policy and Responsibilities: Subject to and expected to comply with all applicable University policies and procedures, including but not limited to the personnel policies and other policies found in the University's Administrative Guide,.

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Classification Title: SLAC Intern Students

Job code: 0901

Intern Level: III

The expected pay range for this position is $21.08 to $35.67 per hour. SLAC National Accelerator Laboratory/Stanford University provides pay ranges representing its good faith estimate of what the university reasonably expects to pay for a position. The pay offered to a selected candidate will be determined based on factors such as (but not limited to) the scope and responsibilities of the position, the qualifications of the selected candidate, departmental budget availability, internal equity, geographic location and external market pay for comparable jobs.

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