RFIC Design Engineer

5 days ago

San Diego, California, United States Apple Full time $120,000 - $180,000 per year
Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

Description
The Wireless SoC Radio Team architects, designs and delivers state-of-art CMOS radios, from RF-to-bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks, such as integrated PAs and LNAs, data converters, mixers, baseband filters, phase-locked loops, crystal oscillators, wideband LDOs and bandgap references. As an RFIC design engineer, you will be at the center of this wireless SoC design group. You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products.

In this highly visibility role, and as part of our team, you will have responsibilities on researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.

Minimum Qualifications
BS and 10+ years of relevant industry experience.
RF/analog and mixed signal design experience in RF CMOS design.

Preferred Qualifications
RFIC circuit design.
Direct tape-out experience with one or more of the following blocks: RF front-end circuits, PA, LNA, mixer, oscillator, PLL, LO, VGA, filter, ADC/DAC, TIA or other baseband analog blocks in deep sub-micron CMOS technology.
Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
Deep understanding of CMOS device physics, RF device modeling, device noise parameters, inductor modeling, and circuit layout for optimum RF performance.
Familiarity with various RF transceiver architectures and their trade-offs.
Familiarity with Cadence Virtuoso, Spectre RF, EMX and similar tools.
Experience in Si characterization and debug.

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