ASIC Manager, Design Verification

2 weeks ago

Sunnyvale, California, United States Meta Full time
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click "Apply to Job" online on this web page.

Responsibilities
Build successful world-class complex SoC and IP for data center applications, and end-to-end SoC/ASIC development. Responsible for firmware and driver development, and front-end and back-end standard cell ASIC development (including algorithm and architectural modeling, silicon architecture, micro-architecture, RTL development). Design Verification, FPGA emulation, co-simulation, simulation acceleration, synthesis, and post-silicon validation. Perform cross-functional collaboration and partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts. Define, debug, implement and deliver system solutions around purpose built ASICs, and create soft and hard IP identification, selection and IP licensing. Provide technical mentorship, plan work assignments, and manage performance reviews for design verification engineers on the team. Domestic and International Travel Required 10%.

Qualifications
Bachelor's degree (or foreign equivalent) in Computer Engineering, Computer Science, Electrical Engineering or related field and 5 years of progressive, post-baccalaureate work experience in the job offered or in a computer-related occupation Experience must include 5 years in the following: One or more HDL languages (System Verilog, Verilog), and one or more scripting languages (TCL, Python, Perl, or Shell-scripting) Standard Cell ASIC development from Architecture through to GDSII release (including pre-silicon emulation and co-simulation) and post-silicon One or more Verification languages (UVM, System Verilog) creating test plans and defining coverage C/C++/SystemC Functional verification based on Simulation-Acceleration EDA tools like VCS, NCSIM, or Verdi

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