Cellular SoC Static Timing Analysis Engineer

2 weeks ago

San Diego, California, United States Apple Full time
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. As part of a world class modem team, you'll be at the heart of chip design Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple's custom silicon. You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations Do you want to have an impact on every single Apple product?

As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.

Description
As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications.

Minimum Qualifications
BS and 3+ years of relevant industry experience.

Hands-on experience in ASIC timing constraints generation and timing closure.

Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.

Good understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing.

Own STA sign-off for block and chip level including custom timing checks.

Hands on experience in timing/SDC constraints generation and management.

Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs.

Proficient in scripting languages (Tcl and Perl/Python).

Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design, DFT, physical design, etc.).

Preferred Qualifications
MS and 3+ years of relevant industry experience.

Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer).

Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.

Solid understanding of timing corners/modes, process variations and signal integrity related issues.

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