Senior RTL Designer
1 week ago
Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.
Job Type:
Contract
Duration:
6+ Months
Location:
Onsite in Santa Clara, CA
Requirement:
5+ years of relevant experience
We are seeking an experienced
ASIC Design Engineer
with deep expertise in
UCIe (Universal Chiplet Interconnect Express)
to join our high-performance silicon design team. The ideal candidate will own the design and integration of UCIe IP at the RTL level, contributing to the development of cutting-edge interconnect and I/O subsystem solutions.
- Own the RTL design
of UCIe IP, including
link, protocol, and PHY interface layers
. - Develop and integrate
Ethernet datapath
and related
interconnect logic
within a broader I/O subsystem. - Design, implement, and verify
RTL modules in SystemVerilog
for ASIC designs. - Collaborate with architecture, verification, and physical design teams to ensure high-quality IP delivery.
- Contribute to
UCIe protocol stack
development, including
link initialization, power management, and flow control
. - Participate in
design reviews, timing analysis, and performance optimization
. - Bachelor's degree or equivalent experience in Design 5+ years of relevant experience
Skills:
- UCIe IP
- RTL Design
- Ethernet Serdes PCIe
- PHY
- SystemVerilog
- Power Management
Benefits:
- Paid weekly
- Health, Dental and Vision Insurance
- 401k
-
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