Digital IC Design Engineer Intern

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As a Digital IC Design Engineer Intern, your responsibilities will include:

• Micro-architecture design and RTL implementation of: 
  • Low-power digital signal processors
  • Low-power general-purpose hardware accelerators
  • Low-power graphics processing units
  • Low-power radio MAC/PHY
  • Low-power serial link MAC/PHY
• Design and implementation of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
  • Complex system modeling for energy and performance benchmarks
  • Workload analysis and modeling
  • Leveraging architecture-level design trade-offs with process technology and workload type
  • Balancing energy efficiency and performance under manufacturing process variation 
• Complex system-on-chip verification
  • Behavioral level modeling and model equivalence check
  • FPGA emulation
  • Analog mixed-signal co-simulation
  • Design for testability 
• Collaboration on silicon bring-up tests with silicon validation engineers 

Required Qualifications:

• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• 2+ years of experience in digital design
• Proficient in SystemVerilog, C/C++, Python
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++, or UVM 
• Experience automating tool flows
• Experience with embedded design
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization
• Experience designing PCBs or writing firmware.

Expected Compensation:

The anticipated hourly rate for this position is listed below.

California Hourly Flat Rate:
$35/Hr USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

• An opportunity to change the world and work with some of the smartest and most talented experts from different fields
• Growth potential; we rapidly advance team members who have an outsized impact
• Excellent medical, dental, and vision insurance through a PPO plan
• Paid holidays
• Commuter benefits
• Meals provided
• Equity (RSUs) *Temporary Employees & Interns excluded
• 401(k) plan *Interns initially excluded until they work 1,000 hours
• Parental leave *Temporary Employees & Interns excluded
• Flexible time off *Temporary Employees & Interns excluded