Senior ASIC VLSI Synthesis and Design Engineer
5 days ago
Our client is looking for a
Senior ASIC/VLSI Synthesis and Design Engineer
to drive the development of high-performance, low-power digital designs for cutting-edge ASICs and SoCs. This role involves optimising power, performance, and area while ensuring timing closure, gate-level simulation, and post-silicon validation. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, and power analysis.
If you have a strong background in ASIC/VLSI design, with deep expertise in synthesis, timing closure, DFT, and post-silicon debug, we want to hear from you.
What you need / Qualifications:
- Bachelor's degree with 8+ years of experience, or Master's degree with 6+ years of experience in Computer Science, Electrical Engineering, Information Technology or a related technical field.
- 5-8+ years of ASIC/VLSI design experience, focusing on synthesis and timing closure for large-scale design in deep submicron technology.
- Expertise in Verilog/SystemVerilog RTL coding and constraint development for synthesis.
- Proficiency in synthesis tools from leading EDA vendors (Cadence, Synopsys, Mentor).
- Experience with gate-level simulation, static timing analysis (STA), and power-aware synthesis.
- Strong post-silicon debug and validation skills, including production bring-up and failure analysis.
- Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimisation.
- Strong problem-solving, debugging, and collaboration skills in a fast-paced environment.
What you'll do:
- Lead the design, synthesis, and implementation of high-performance, low-power digital circuits for advanced ASIC and SoC products.
- Develop and optimise RTL-level designs using Verilog/SystemVerilog to achieve performance, power, and area (PPA) targets.
- Perform synthesis, timing closure, and constraint development using industry-standard EDA tools (Synopsys, Cadence, Mentor).
- Conduct static timing analysis (STA) and gate-level simulations to ensure functional and timing integrity across all design stages.
- Collaborate closely with architecture, verification, and physical design teams to define design methodologies and resolve timing and functional issues.
- Drive power-aware synthesis and optimisation, ensuring compliance with power budgets and low-power design techniques.
- Integrate and verify Design-for-Test (DFT) features, working with DFT engineers to ensure testability and robust silicon performance.
- Support post-silicon validation and debug, including bring-up, failure analysis, and correlation between pre-silicon and silicon behaviour.
- Develop and maintain automation scripts and flows (Tcl, Perl, Python) to streamline synthesis and verification processes.
- Participate in design reviews, provide technical guidance to junior engineers, and contribute to continuous process improvement initiatives.
ONE Technology Services
We specialise in staffing and software development services, including custom app development, custom web development, staff augmentation, managed and cloud solutions, technical recruitment, and IT consultancy.
ONE Technology Services
is also a product-based company. Our products, Workshop solution and ERP solution for services-based businesses, are already well-tested and solve business problems by hitting right in the bull's eye. These products are highly customizable to address the specific needs of our clients. Having 20+ years of industry experience with top US and Canadian companies enables us to know exactly how to solve all our clients' business challenges.
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