ASIC Power Engineer
2 days ago
Role Number: 200628186-3401
Summary
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient / low-power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams.
Description
In this highly visible role, you will be at the center of low-power architecture, power modeling and correlation efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. You will work on power modeling, analysis and correlation tasks for wireless communication SoCs.
Will you join us and do the best work of your life here?
Minimum Qualifications
-
Minimum requirement of a bachelors degree.
-
ASIC power knowledge.
-
Experience with Power tools, e.g. PTPX and Power Artist.
-
Understand ASIC logic design.
-
Knowledge of low power design and UPF.
-
Proficiency in scripting languages (Shell, Perl or Python).
-
Basic knowledge on common SOC components, e.g. CPU, fabric, peripherals and PCIe.
-
Strong problem solving and analytical skills.
Preferred Qualifications
-
Pre-silicon power estimation experience.
-
Pre-silicon Power modeling experience.
-
Actual low power design experience.
-
Wireless knowledge, including WIFI, BT and UWB.
-
ASIC PD, STA knowledge.
-
System architecture experience.
-
In depth knowledge of common SOC components, e.g. CPU, fabric, peripherals and PCIe.
-
Post-silicon functional debug and power correlation experience.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf) .
-
Senior ASIC Engineer
2 weeks ago
San Jose, CA, United States Top Engineer Full timeTOP ENGINEER JOB POST!!! Confidential Search for International Employer Industry: Electronics / Semiconductors Degree: BSEE Required (MSEE Preferred) Experience: 10+ years with Full ASIC/SoC Lifecycle CUTTING-EDGE CUSTOM ASICs & SOCs FOR EMERGING TECHNOLOGIES Role: Senior ASIC Engineer - ARM-Based Systems Join a cutting-edge developer of custom ASICs...
-
San Francisco, CA, United States Apple Full timeRole Number: 200628043-3401 Summary Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an...
-
Senior ASIC Design Engineer
2 weeks ago
San Francisco, CA, United States Ethan Alexander Group, Inc. Full timeASIC Design EngineerResponsibilities:Define and bring up FPGA platforms for pre-silicon validation and software development Map ASIC RTL to FGPA while minimizing code base differences Create and execute test plans for validating SoC functionality and performance Resolve challenging system level issues that span multiple disciplines Design logic starting from...
-
Senior ASIC Design Engineer
2 days ago
San Francisco, CA, United States Ethan Alexander Group, Inc. Full timeASIC Design EngineerResponsibilities:Define and bring up FPGA platforms for pre-silicon validation and software development Map ASIC RTL to FGPA while minimizing code base differences Create and execute test plans for validating SoC functionality and performance Resolve challenging system level issues that span multiple disciplines Design logic starting from...
-
ASIC Methodology Engineer
6 days ago
San Diego, CA, United States Qualcomm Full timeCompany: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization...
-
ASIC Methodology Engineer
2 weeks ago
San Diego, CA, United States Qualcomm Full timeCompany: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization...
-
ASIC Methodology Engineer
1 week ago
San Diego, CA, United States Qualcomm Full timeCompany: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization...
-
ASIC Methodology Engineer
1 week ago
San Diego, CA, United States Qualcomm Full timeCompany: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization...
-
ASIC Methodology Engineer
2 weeks ago
San Diego, CA, United States Qualcomm Full timeCompany: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization...
-
Principal Engineer, ASIC Physical Design
2 weeks ago
San Jose, CA, United States Ayar Labs Full timePrincipal Engineer, ASIC Physical Design Location: San Jose (on-site) The ASIC Physical Design Engineer is responsible for the physical design and integration of complex SoCs with custom circuits, digital circuits, and photonics components as part of a high-speed electro-optical engine. The position focuses on the synthesis, place and route, timing closure,...
