Senior Hardware/Firmware Engineer

2 weeks ago


Boulder, CO, United States Microsoft Corporation Full time
Overview

Do you want to be at the forefront of innovating the latest hardware designs to propel Microsoft's cloud growth? Are you seeking a unique career opportunity that combines technical capabilities,cross-teamcollaborationwith business insight and strategy?

Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees, we come together with a growth mindset, innovate to empower others, and collaborate to achieve our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positivelyimpactour culture every day.

Join theSystemsPlanning and Architecture(SPARC) team within Microsoft's Azure Hardware Systems and Infrastructure (AHSI) organization, the team behind Microsoft's expanding Cloud Infrastructureand for poweringMicrosoft's "Intelligent Cloud" mission.Microsoft delivers more than 200 online services to more than one billion individualsworldwide,and AHSI is the team behind our expanding cloud infrastructure. We deliver the core infrastructure and foundational technologies for Microsoft's cloud businesses including Microsoft Azure, Bing, MSN, Office 365, OneDrive, Skype,Teamsand Xbox Live.

The SPARC organization manages Azure's hardware roadmap from architecture concept through production for all of Microsoft's current and future on-line services.This role is for a highly motivatedHardware/FirmwareEngineer with a background in design and development.You will be involved with all phases of product development, from secure silicon design through manufacturing and supply chain, and into high scale deployment.At the design phase, you will work with security&platform infrastructure teamsandbe responsible fortheinfrastructure managementarchitecture and developing the solution fromsilicon to platform.

We are looking for a Senior Hardware/ Firmware Engineer to join our team

Responsibilities
  • ArchitectCPU or GPU computeinfrastructures as well as newer security technologies.
  • Understand& evaluatethe architectural choices& theirimpacttoplatform infrastructure.
  • Develop production quality (BMC, BIOS) FW to prove various prototypes.
  • Work with open-ended problem statementsandidentifyproblem statements themselves.


Qualifications

Required/minimum qualifications

  • Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience OR equivalent experience.
  • 4+ years of experience in betweenCPU/GPU/Platform architecture,design & validation.
  • 4+ years of experience in firmware and software, collaborating seamlessly with FW/SW teams to architect and design optimal solutions.
  • 4+ years of experience in USB architectural expertise & experience and ability to understand, developandoptimizethe USBdriverFW.
  • 4+ years of experience and expertisein pre-silicon HW design andvalidationOR ability to develop/debug platform level (FW/HW) interactions.Laterone has more weightage for this role.

Other Requirements:

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional or preferred qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience.
  • Good understanding ofnewerplatform architectures is a plus
  • Proven and demonstrableskillinC/C++ and Python; Knowledge of Rust is good to have.
  • Familiarity with PCIe TDISP architecture is a plus but notrequired.
  • Wear multiple hats to seamlessly transition between architecture& development

#AHSI #SPARC

Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.



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