Senior ASIC Design Verification Engineer

6 days ago

San Jose, CA, United States Ethernovia, Inc. Full time
About Ethernovia, Inc.

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we're inventing the future of automobile's communication We are transforming automobiles' communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car's cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds' leading technology investors, having secured $64m in Series A funding. (Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire). Our financial backers include Porsche SE, Qualcomm, AMD, and Western Digital

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com)

September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia

Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news

With talented employees on 4 continents, we have filed > 50 patents to date.

Join Ethernovia's team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car.

Senior ASIC Design Verification Engineer

Summary:
  • As a Senior ASIC Verification Engineer, you will be responsible for all aspects of digital SoC verification.
  • You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
  • You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.
  • This position is located in: San Jose, CA
Key Qualifications:
  • BS and/or MS in Electrical Engineering, Computer Science, or related field
  • Minimum 10+ years of ASIC verification experience
  • Strong understanding of ASIC verification fundamentals and industry standard methodologies
  • Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
  • Experience with the full verification flow, from spec to coverage analysis to gate level sim
  • Debugging failures in simulation to root cause problems
  • Self-motivated and able to work effectively both independently and in a team
Additional Success Factors:Experience in any of the following areas:
  • Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
  • Video standards, protocols, processing
  • Digital signal processing filters
  • Third party IP (SerDes, controllers, processors, etc.)
  • Modular and Reusable Testbench architecture
  • Design for re-use of pre and post silicon tests and infrastructure
  • Automation of testbench creation, tests, regression, or EDA tools
  • Knowledge of SystemC and/or DPI
Personal Skills:
  • Excellent communication/documentation skills.
  • Attention to details.
  • Collaboration across multidisciplinary and international teams.
What You Can Expect from Ethernovia:
  • Technology depth and breadth expansion that can't be found in a large company
  • Opportunity to grow your career as the company grows
  • Pre IPO stock options
  • Cutting edge technology
  • World class team
  • Competitive base salary
  • Flexible hours
  • Medical, dental and vision insurance for employees
Salary Range:
  • The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

  • Senior ASIC Engineer

    21 hours ago

    San Jose, CA, United States Top Engineer Full time

    TOP ENGINEER JOB POST!!! Confidential Search for International Employer Industry: Electronics / Semiconductors Degree: BSEE Required (MSEE Preferred) Experience: 10+ years with Full ASIC/SoC Lifecycle CUTTING-EDGE CUSTOM ASICs & SOCs FOR EMERGING TECHNOLOGIES Role: Senior ASIC Engineer - ARM-Based Systems Join a cutting-edge developer of custom ASICs and...

  • Senior ASIC Design Engineer

    5 days ago

    San Jose, CA, United States P. Chappel Associates Inc Full time

    Our client, a cutting-edge developer of custom ASICs and SoCs for emerging technologies, is seeking a Senior ASIC Design Engineer to join their growing team in San Jose. This role is ideal for engineers with stable work histories , strong customer-facing experience , and a track record of owning the full ASIC/SoC lifecycle -from initial specifications...

  • Senior ASIC Design Engineer

    6 days ago

    San Jose, CA, United States P. Chappel Associates Inc Full time

    Our client, a cutting-edge developer of custom ASICs and SoCs for emerging technologies, is seeking a Senior ASIC Design Engineer to join their growing team in San Jose. This role is ideal for engineers with stable work histories , strong customer-facing experience , and a track record of owning the full ASIC/SoC lifecycle -from initial specifications...

  • ASIC Design Verification Engineer.

    1 week ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • ASIC Design Verification Engineer.

    2 weeks ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • ASIC Design Verification Engineer.

    7 days ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • ASIC Design Verification Engineer.

    2 weeks ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • ASIC Design Verification Engineer.

    2 weeks ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • ASIC Design Verification Engineer.

    8 hours ago

    San Francisco, CA, United States Kasmo Global Full time

    Job Title: ASIC Design Verification Engineer. Location: Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area Required Experience: 6+ Years. Work Authorizations: Preferably GC and US citizens. h1b all visa need 1.5 years validity work authorization, drivers license and references LinkedIn proper *** need local ...

  • Principal Engineer, ASIC Design Verification

    7 days ago

    San Jose, CA, United States Ayar Labs Full time

    Principal Engineer, ASIC Design Verification Location: San Jose (on-site) We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high-quality silicon from concept to...