Senior R&D Engineer, Electrical

TITLE

Sr. R&D Engineer, Electrical & FPGA Design

DATE

October 2026

WORK LOCATION

In-Office 5x/week in San Diego

BASE SALARY RANGE

$140,000 - $180,000/year

About the Role

We are seeking a Senior R&D Electrical Engineer to own the electrical and programmable-logic design of Synchron's next-generation implantable electronics, from concept through design verification. The core of the role is defining and developing the HDL for the implant's low-power FPGA: supervisory logic for device health, status, and control, and the implant side of a high-speed serial link to distributed sensing electronics, defined from interface specifications with external silicon partners and proven in FPGA emulation ahead of hardware. The role also owns the surrounding electrical architecture - custom silicon integration, inductive charging and RF telemetry, and PCB/flex design - and carries a safety mandate: detectable faults, redundant monitoring, and defined safe states within a medical device design-controls framework.

Firmware is owned by a dedicated engineer; this role reviews, debugs, or contributes to firmware and test software as the program needs. This is a hands-on, technically deep role: equally comfortable reviewing RTL and schematics as defining system-level architecture.

Key Responsibilities

FPGA / HDL Design

• Architect and develop synthesizable HDL (VHDL or SystemVerilog) for a low-power FPGA serving as the implant's health, status, control, and communications controller; select the FPGA family and configuration approach against power, size, I/O, and configuration-integrity constraints
• Implement supervisory functions: power sequencing, voltage/current/temperature monitoring, watchdogs, fault detection and latching, status reporting to the host MCU, and transition to defined safe states
• Own timing closure, clock-domain crossing, and low-power clocking; develop self-checking testbenches and simulation regressions appropriate to safety-relevant logic
• Define and verify the FPGA/MCU interface (SPI, register map); own FPGA bring-up, diagnostics, and configuration/update strategy

High-Speed Sensor Communications Link

• Define and implement the implant side of the serial link to distributed sensing electronics: clock generation and distribution, line driver/receiver scheme (including emulated-LVDS I/O), framing, synchronization, error detection, and recovery
• Derive and maintain link and timing budgets (jitter, skew, channel loss) and reconcile them with partner models
• Build bench models and FPGA emulation of the link, integrating partner-supplied RTL, to retire risk before final hardware

Safety & Redundant Systems

• Design control and monitoring logic so single faults are detected and contained: redundant or diverse monitors, FPGA/MCU cross-checks, independent shutdown paths, and fail-safe defaults on loss of clock, power, or communication
• Define safe-state behavior and entry/exit conditions; perform FMEA / fault-tree analysis and trace risk controls to design inputs and verification per ISO 14971
• Apply configuration-integrity and single-event-upset mitigations (CRC, readback, redundancy) for chronically implanted programmable logic

Electrical Architecture, Power & RF

• Own the implant's electrical architecture and lead schematic design, component selection, and simulation for ultra-low-power implantable electronics
• Design and characterize the inductive charging link: receive coil geometry and placement, resonant tuning, rectification and regulation, alignment and load tolerance, and tissue heating limits
• Optimize the wireless telemetry link (custom RF, BLE, or inductive) under tissue constraints, including antenna selection, matching, and integration within the hermetic enclosure and header
• Establish power budgets and duty-cycling strategies that balance data throughput against implant longevity

PCB/Flex, Verification & Design Controls

• Lead design of miniaturized, high-density PCB and flex-rigi