Design Verification Engineer

Introduction to the jobWe are looking for a Design Verification Engineer to serve as a technical leader driving verification strategy and execution for highly complex FPGA designs. This role will architect advanced verification environments, define methodologies, and ensure best-in-class quality for ASML’s EUV Source systems. It requires deep technical expertise, leadership in verification practices, and the ability to influence design and verification decisions across teams.Role and responsibilitiesDefine and own verification strategy for large-scale, multi-block FPGA systems.Architect and implement advanced, reusable verification environments using SystemVerilog UVM and UVMF.Develop sophisticated test benches, constrained-random tests, and coverage models to achieve full functional and code coverage.Drive requirement traceability and compliance through robust documentation and reporting.Collaborate with architects, design engineers, and cross-functional teams to ensure design integrity and verification completeness.Lead debug efforts for complex system-level issues and root-cause analysis.Establish and enforce best practices for verification methodology, automation, and regression management.Mentor and guide junior and mid-level engineers; provide technical leadership and training.Influence tool adoption, methodology improvements, and process optimization across the organization.Other duties as assigned.Software Engineer 3- Education and ExperienceBachelors’ degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.2+ years’ experience with a Bachelor’s degree.0 + years’ experience with a Master’s degree.Understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.Experience with UVM for modular and reusable verification IP development.Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.Senior Software Engineer 1 - Education and ExperienceBachelors’ degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.5+ years’ experience with a Bachelor’s degree.2 + years’ experience with a Master’s degree.1+ years’ experience with a PhD.Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management.Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.Experience with UVM for modular and reusable verification IP development.Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.Senior Software Engineer 2 - Education and experienceBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.8+ years’ experience with a Bachelor’s degree.5 + years’ experience with a Master’s degree.3+ years’ experience with a PhD.Must possess industry experience in FPGA design verification; equivalent experience in ASIC workflows acceptable.Proven track record of leading verification for complex SoC or FPGA systems, including hardware bring-up and test.Expert-level proficiency in SystemVerilog UVM, including architecting environments and building custom components from scratch.Extensive experience with simulation tools (e.g., QuestaSim, VCS, or similar) and regression management.Strong understanding of coverage-driven verification, constrained-random methodologies, and assertion-based verification.Deep experience with UVM for modular and reusable verification IP development.Familiarity with CI/CD pipelines, version control systems (Git), and continuous integration frameworks.Preferred:Proficiency in scripting languages (Python, Perl, or similar) for automation and flow optimization.Experience with UVMF for modular and reusable verification environments.Exposure to formal verification techniques and advanced debug methodologies.SkillsAbility to architect and optimize complex verification environments for scalability and reuse.Advanced problem-solving and debugging skills for system-level and multi-block designs.Strong leadership and mentoring capabilities; able to guide teams and influence technical direction.Excellent communication and collaboration skills for cross-functional engagement.Expertise in coverage analysis and closure strategies.Strong organizational and planning skills for managing large verification projects.Experience driving methodology improvements and automation initiatives.Familiarity with FPGA-specific verification strategies and hardware validation.Ability to innovate and implement process enhancements for efficiency and quality.Other InformationThis position is located on-site in San Diego, CA . It requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation.A flexible workplace arrangement may be available to employees working in roles conducive to remote work (up to two days a week).Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. Occasionally required to move around the campus.Occasionally lift and/or move up to 20 pounds.Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.Must be willing to work in a clean room environment, wearing coveralls, hoods, booties, safety glasses and gloves for entire duration of shift.While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.EOE AA M/F/Veteran/DisabilityThe current base annual salary range for this role is currently:$0-0Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members.The Company offers employees and their families, medical, dental, vision, and basic life insurance. Employees are able to participate in the Company’s 401k plan. Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year. For more information, please contact the Recruiter or click on this link .All new ASML jobs have a minimum application deadline of 10 days.Inclusion and diversityASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.Need to know more about applying for a job at ASML? Read our .Request an AccommodationASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and/or enjoy equal access to the benefits and privileges of employment. If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to to initiate the company’s reasonable accommodation process.