Senior Memory Design Engineer

4 weeks ago


Santa Clara, California, United States Rival Inc Full time
Rivos Custom Circuits Team Seeks Expert Memory Designers

We are seeking highly motivated candidates to develop cutting-edge custom SRAM memories, register file memories, and compiled memories to enhance circuit performance, optimize dynamic and static power, and support silicon bring-up.

The ideal candidate will be at the center of a state-of-the-art circuit design effort, collaborating with all disciplines and having a critical impact on getting products to market quickly.

Key Responsibilities
  • Design and deliver custom circuits from scratch
  • Develop state-of-the-art custom SRAM memories, register file memories, and compiled memories
  • Conduct early sizing estimates and PPA analysis
  • Design entry and simulations for optimal design sizing
  • Work closely with mask designers on custom design implementation, DFM, and yield enhancement features
  • Deliver high-quality design collateral
  • Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing, and power closure of the custom design
  • Interact with technology teams and participate in developing design and test plans
Requirements
  • Master's Degree or Bachelor's Degree with 8-10 years of experience
  • 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking, PPA trade-off analysis, low power design techniques, timing, noise, and power characterization
  • 10 years of custom circuit design experience from RTL-GDS for CPU and SoC applications
  • Prior experience and proven success of successfully designing high-performance SRAM memories, register file memories, SRAM compilers, data path designs, and standard cells
  • Experience designing transistor-level custom circuits in advanced FinFET technology nodes
  • Solid experience with custom circuit tool flows for delivering design collaterals
  • Solid understanding of device physics, process technology, and circuit design techniques for high-performance, low-power designs
  • Experience with advanced process design rules and supervising mask design
  • Knowledge developing automation for compilers and standard cells
  • Post-Silicon test and debug experience
  • Ability to work well in a team and be productive under aggressive schedules
  • Excellent problem-solving, written, and verbal communication


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