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Principal Engineer in CAD Methodology

2 months ago

Mountain View, California, United States Synopsys Full time
Job Overview and Requirements

At Synopsys, our Silicon IP division focuses on enhancing the capabilities of System on Chips (SoCs) at an accelerated pace. We provide an extensive range of silicon IP solutions, including pre-designed logic blocks, memory, interfaces, analog components, security features, and embedded processors. Our goal is to assist clients in integrating advanced functionalities, meeting specific performance, power, and size criteria for their applications, and delivering unique products to market swiftly while minimizing risks.

We are at the forefront of innovations that transform everyday life, from self-driving vehicles to artificial intelligence, cloud computing, 5G technology, and the Internet of Things. These advancements are leading us into the Era of Smart Everything, and we are powering these innovations with the most sophisticated technologies in chip design and software security. If you are passionate about innovation, we would like to connect with you.

Position: Principal Engineer in CAD Methodology

Key Responsibilities:
  • Recommend process, voltage, and temperature parameters, along with corner selection for assigned projects.
  • Establish a methodology for Timing Signoff, incorporating POCV settings, margining strategies (jitter/setup/hold margins), and ensuring correlation between implementation and signoff tools.
  • Facilitate the enablement of new technologies for design services, including pathfinding for new nodes, radiation hardening (A&G programs), and autograde signoff criteria.
  • Own the methodology and templates for timing constraints, ensuring comprehensive generation for all operational modes.
  • Manage low power methodologies, including UPF template ownership and conducting ramp-up/ramp-down IR drop analyses.
  • Develop and oversee methodologies for high-performance custom power grids, high-speed custom clock trees, decap, EMIR, ESD, and Spice analysis of clock trees.
  • Support ongoing projects with enhancements in performance, power, and area.
  • Interface with foundries regarding tapeout processes, including PDK, mock-tapeouts, and e-job views.
Essential Skills:
  • Deep understanding of the ASIC development lifecycle and full-chip SoC flows.
  • Familiarity with all Synopsys EDA tools utilized in RTL to GDS flows.
  • Proficient in developing algorithms and scripts aimed at high-speed performance and low-power design methodologies.
  • Knowledgeable about emerging chip design technologies, including chiplets, D2D interfaces, and 3D ICs.
  • Exceptional programming skills in languages such as C, C++, Python, Perl, and TCL for automation purposes.
  • Extensive experience collaborating across various functional teams.
  • Experience in a customer-focused environment.
Qualifications:
  • A minimum of 12 years of relevant industry experience.
  • A Bachelor's or Master's degree in Electrical Engineering.
The salary range for this position across the U.S. is between $159,000 and $239,000. Additionally, this role may qualify for an annual bonus, equity, and other discretionary bonuses. Synopsys provides a comprehensive benefits package that includes health, wellness, and financial benefits as part of a competitive total rewards offering. The specific compensation will be determined based on various job-related factors, including location, skills, experience, and education. Your recruiter can provide more detailed information regarding the total rewards package upon request.

We value Inclusion and Diversity at Synopsys and consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.